Detecting asymmetrical transistor leakage defects
View Patent ↗A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.
1. A method of detecting asymmetric leakage in an array of field-effect transistors, each having a channel, a source diffusion on one side of the channel, and a drain diffusion on another side of the channel, the method comprising:
connecting together a first side of all of the transistors in common with first side connections;
connecting together a second side of all of the transistors in common with second side connections;
applying a biasing voltage across the first and second side connections;
measuring a first leakage current between the commonly connected first and second side connections;
reversing the biasing voltage across the first and second side connections;
measuring a second leakage current between the commonly connected first and second side connections; and
comparing the first and second leakage current measurements.
2. The method of claim 1 , including:
connecting gate terminals of all of the transistors in common and applying an off-state voltage to the common gate connection.
3. The method of claim 1 , including:
forming a junction at each diffusion with the channel; and
causing asymmetrical leakage resulting from a diffusion defect, a silicide defect, or a substrate defect affecting one junction and not the other.
4. The method of claim 1 , including:
causing the asymmetrical leakage by layout-sensitive defects.
5. The method of claim 1 , wherein:
the method of detecting leakage comprises swapping the biasing voltage polarity while measuring leakage current in one direction and the opposite direction and comparing the difference of current-voltage curves measured in order to detect the leakage current.