IP Library Granted Patent US 8,377,813
Granted Patent B2
US 8,377,813 · App. 12/870,612 · Granted Feb 19, 2013

Split word line fabrication process

Inventor: Chih-Hao Lin (Taichung, TW)
Assignee: Rexchip Electronics Corporation
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Quick Facts
Patent No.
US 8,377,813
App. No.
12/870,612
Granted
Feb 19, 2013
Kind
B2
Abstract

A method for forming a buried split word line structure is provided. The method comprises the following steps. At first, a substrate having a trench therein is provided. Two liners are formed to a first thickness on sidewalls of the trench. Then, the trench is filled with a first insulating layer to a first height. The two liners are removed. Finally, a conductive material is deposited to a second height between and adjacent to the first insulating layer and the trench. Here, the first height is greater than the second height.

Claims (47)

1. A method for forming a buried split word line structure, comprising:

providing a substrate having a trench therein;

forming a conductive material conformal to the trench;

depositing a first insulating layer within the trench adjacent the conductive material;

etching the first insulating layer to a first etched depth;

etching the conductive material to a second etched depth in accordance with the first etched depth to thereby form a U-shaped gate conductor;

depositing a second insulating layer above the U-shaped gate conductor and conformal to the trench; and

etching away portions of a third insulating layer, the U-shaped gate conductor and the substrate to form a recess in substrate so that the U-shaped gate conductor is split into two halves;

wherein the third layer is formed above the U-shaped gate conductor and the second etched depth is greater than the first etched depth.

2. The method according to claim 1 , wherein the step of forming the conductive layer comprises:

forming a fourth insulating layer to a first thickness conformal to the trench;

forming a glue layer to a second thickness over the fourth insulating layer; and

forming the conductive material to a third thickness over the glue layer.

3. The method according to claim 2 , wherein the step of forming the conductive material to the third thickness over the glue layer comprises forming the conductive material to the third thickness over the glue layer by atomic layer deposition (ALD).

4. The method according to claim 2 , wherein the first thickness, the second thickness and the third thickness are related to a width of the buried split word line structure.

5. The method according to claim 1 , wherein the second etched depth determines a height of the split word line structure.

6. The method according to claim 1 , wherein the second insulating layer is deposited further above the first insulating layer and the third insulating layer comprises the first insulating layer and the second insulating layer.

7. The method according to claim 1 , wherein the step of etching the conductive material comprises:

etching the glue layer to the second etched depth; and

etching the conductive material to the second etched depth to thereby form the U-shaped gate conductor, wherein the surface of the glue layer is substantially coplanar with the surface of the U-shaped gate conductor.

8. The method according to claim 1 , wherein the second etched depth increases as the first etched depth decreases.

9. The method according to claim 1 , further comprising:

removing the first insulating layer before depositing the second insulating layer;

wherein the third insulating layer comprises the second insulating layer.

10. A method for forming a buried split word line structure, comprising:

providing a substrate having a trench therein;

forming two liners to a first thickness on sidewalls of the trench;

filling the trench with a first insulating layer to a first height;

removing the liners; and

depositing a conductive material to a second height between and adjacent to the first insulating layer and the trench;

wherein the first height is greater than the second height.

11. The method according to claim 10 , wherein the step of forming the two liners comprises:

filling the trench with a second insulating layer to a second thickness;

forming a hard mask conformal to the trench and the second insulating layer to a third thickness; and

etching away portions of the second insulating layer, the hard mask and the substrate to form a recess in the substrate;

wherein a first material that forms the first insulating layer is different from a second material that forms the second insulating layer.

12. The method according to claim 10 , wherein the first thickness is related to a thickness of the conductive material.

13. The method according to claim 11 , wherein the third thickness is related to a thickness of the conductive material.

14. The method according to claim 11 , wherein the step of forming the hard mask comprises forming the hard mask conformal to the trench and the second insulating layer to the third thickness by atomic layer deposition (ALD).

15. The method according to claim 10 , wherein the step of forming the two liners comprises:

forming a second insulating layer conformal to the trench to a second thickness; and

etching away portions of the second insulating layer and the substrate to from a recess in the substrate;

wherein the first insulating layer and the second insulating layer are different.

16. The method according to claim 15 , wherein the first thickness is substantially equal to the second thickness.

17. The method according to claim 15 , wherein the second thickness is related to a thickness of the conductive material.

18. The method according to claim 15 , wherein the step of forming the second insulating layer comprises forming the second insulating layer conformal to the trench to the second thickness by atomic layer deposition (ALD).

19. The method according to claim 10 , wherein each of the two liners comprises at least one layer.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: MICRON MEMORY TAIWAN CO., LTD.,
To: MICRON TECHNOLOGY, INC
Reel/Frame 037222/0690 →
CHANGE OF NAME Recorded Dec 7, 2015
From: REXCHIP ELECTRONICS CO., LTD.
To: MICRON MEMORY TAIWAN CO., LTD.
Reel/Frame 037223/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2010
From: LIN, CHIH-HAO
To: REXCHIP ELECTRONICS CORPORATION
Reel/Frame 024902/0453 →
Continuity (1)
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