IP Library Granted Patent US 8,409,921
Granted Patent B2
US 8,409,921 · App. 12/834,176 · Granted Apr 2, 2013

Integrated circuit package system including honeycomb molding

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,409,921
App. No.
12/834,176
Granted
Apr 2, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts.

Claims (47)

1. A method of manufacture of an integrated circuit package system comprising:

providing a substrate with a top surface;

configuring the top surface to include electrical contacts and an integrated circuit;

providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and

depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits exposing the electrical contacts.

2. The method as claimed in claim 1 further comprising:

configuring each of the discrete hollow conduits for receiving an electrical connection.

3. The method as claimed in claim 1 further comprising:

forming an electrical connection within the discrete hollow conduits contacting the electrical contacts.

4. The method as claimed in claim 1 further comprising:

forming a de-gate structure on the substrate.

5. The method as claimed in claim 1 further comprising:

configuring the structure to include two or more of a unit cell.

6. The method as claimed in claim 1 wherein:

configuring the top surface to include an integrated circuit includes providing two or more of the integrated circuits; and

depositing the material includes depositing via a side mold system.

7. The method as claimed in claim 6 further comprising:

configuring the discrete hollow conduits to include a stepped configuration.

8. The method as claimed in claim 6 further comprising:

forming external electrical connections on a bottom surface of the substrate.

9. The method as claimed in claim 6 further comprising:

configuring the integrated circuit package system to include a package-on-package configuration or a package-in-package configuration.

10. The method as claimed in claim 6 further comprising:

configuring the discrete hollow conduits to be larger than the electrical contacts.

11. A method of manufacture of an integrated circuit package system comprising:

providing a substrate with a top surface;

configuring the top surface to include electrical contacts and an integrated circuit;

providing a structure over the substrate with only a protruding block contacting the top surface of the substrate; and

depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have a block conduit exposing the electrical contacts.

12. The method as claimed in claim 11 further comprising:

configuring each of the block conduits to include two or more rows of the electrical contacts.

13. The method as claimed in claim 11 further comprising:

forming an electrical connection within the block conduits contacting the electrical contacts.

14. The method as claimed in claim 11 further comprising:

forming a de-gate structure on the substrate.

15. The method as claimed in claim 11 further comprising:

configuring the protruding block to include a trapezoidal shape.

16. The method as claimed in claim 11 further comprising:

forming two or more of the protruding block around the integrated circuit.

17. The method as claimed in claim 16 further comprising:

configuring the protruding blocks to form mold pathways.

18. The method as claimed in claim 16 wherein:

forming external electrical connections on a bottom surface of the substrate.

19. The method as claimed in claim 16 further comprising:

configuring the integrated circuit package system to include a package-on-package configuration or a package-in-package configuration.

20. The method as claimed in claim 16 further comprising:

forming an outer mold cap ring for support.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2010
From: KUAN, HEAP HOE; ESLAMPOUR, HAMID; CHOI, DAESIK; HUANG, RUI; LIM, TAEG KI
To: STATS CHIPPAC LTD.
Reel/Frame 024749/0405 →