IP Library Granted Patent US 8,470,657
Granted Patent B1
US 8,470,657 · App. 13/532,293 · Granted Jun 25, 2013

Ion implantation method for semiconductor sidewalls

Inventor: Chih-Hsin Lo (Taichung, TW)
Assignee: Rexchip Electronics Corporation
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Quick Facts
Patent No.
US 8,470,657
App. No.
13/532,293
Granted
Jun 25, 2013
Kind
B1
Abstract

An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.

Claims (24)

1. An ion implantation method for semiconductor sidewalls, comprising the steps of:

S 1 : forming at least one trench on a substrate, the at least one trench including an opening, a bottom section far away from the opening, a lower reflecting layer formed on the bottom section, and two sidewalls adjacent to the bottom section;

S 2 : performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer, and the conductive ions being rebounded from the lower reflecting layer to adhere to the two sidewalls to respectively form an adhesion layer thereon; and

S 3 : performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment.

2. The ion implantation method of claim 1 , wherein the substrate is formed by sequentially depositing a semiconductor layer and an insulating layer.

3. The ion implantation method of claim 2 , wherein the semiconductor layer is made of silicon and the insulating layer is made of silicon nitride.

4. The ion implantation method of claim 1 , wherein the trench is formed at a depth greater than ten times of a width of the trench.

5. The ion implantation method of claim 1 , after the Step S 1 , further comprising the steps of:

S 1 A: forming at least one protection layer on surfaces of the substrate and the at least one trench; and

S 1 B: forming the lower reflecting layer at the bottom section of the at least one trench, and forming two doping sidewalls at positions where the two sidewalls are adjacent to the lower reflecting layer.

6. The ion implantation method of claim 5 , wherein in the Step S 1 A, an oxidation protection layer and a silicon nitride protection layer are sequentially deposited on the surfaces of the substrate and the at least one trench to form the protection layer.

7. The ion implantation method of claim 5 , wherein in the Step S 2 , the conductive ions are deposited in coordination with an inert gas, and the inert gas impacts the conductive ions deposited on the lower reflecting layer to allow the conductive ions to be rebounded to adhere to one of the two doping sidewalls to form the adhesion layer.

8. The ion implantation method of claim 1 , wherein in the Step S 2 , the conductive ions are made of hydrogen arsenide or hydrogen phosphide.

9. The ion implantation method of claim 7 , between the Steps S 2 and S 3 , further comprising the step of:

S 2 A: oxidizing a surface of the adhesion layer to form an oxidation adhesion layer.

10. The ion implantation method of claim 9 , after the Step S 3 , further comprising the step of:

S 4 : removing the oxidation adhesion layer by etching.

11. The ion implantation method of claim 7 , between the Step S 2 and S 3 , further comprising the step of:

S 2 B: depositing an oxidation layer on the surface of the adhesion layer.

12. The ion implantation method of claim 11 , after the Step S 3 , further comprising the step of:

S 4 : removing the oxidation layer by etching.

13. The ion implantation method of claim 11 , wherein the oxidation layer is formed by atomic layer deposition (ALD) or molecular layer deposition (MLD).

14. The ion implantation method of claim 1 , wherein in the Step S 1 , the lower reflecting layer is formed on the bottom section of the at least one trench by a spin-on dielectric (SOD) material.

15. The ion implantation method of claim 1 , further comprising a plurality of trenches and a plurality of posts each being disposed between any two of the plurality of trenches, and the conductive segment is formed on one of the plurality of posts.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: MICRON MEMORY TAIWAN CO., LTD.,
To: MICRON TECHNOLOGY, INC
Reel/Frame 037222/0690 →
CHANGE OF NAME Recorded Dec 7, 2015
From: REXCHIP ELECTRONICS CO., LTD.
To: MICRON MEMORY TAIWAN CO., LTD.
Reel/Frame 037223/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2012
From: LO, CHIH-HSIN
To: REXCHIP ELECTRONICS CORPORATION
Reel/Frame 028438/0629 →