Cache directory look-up re-use as conflict check mechanism for speculative memory requests
View Patent ↗In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.
1. In a cache memory of a data processing system, a method comprising:
receiving a plurality of memory access requests;
queuing the requests;
checking a given one of requests against at least one entry in a cache directory to yield a memory access request related result;
storing at least one such result; and
responsive to a subsequent one of the requests, using the stored result rather than checking the cache directory to find the result, wherein
the cache memory serves as a point of coherence for a multiprocessor system, said cache directory including records of memory access requests from speculative threads in the multiprocessor system, said requests checking comprising:
using the directory to detect conflicts between speculative threads; and
using the stored result allows skipping checking for conflicts between speculative threads.
2. The method of claim 1 , comprising: responsive to the given request, detecting the subsequent request as relating to a same location in the cache as the given request and wherein using the stored result is also responsive to such detecting.
3. The method of claim 1 , comprising,
responsive to the queuing, detecting memory accesses using a same cache resource; and
reordering the requests within the queue so that the given and subsequent request are immediately adjacent one another.
4. The method of claim 1 , wherein the result is an indication of a particular cache resource.
5. The method of claim 4 , wherein the particular cache resource is a way of the cache.
6. The method of claim 1 , wherein the result is data retrieved from a cache resource.
7. The method of claim 1 , wherein storing comprises retaining a plurality of such results at the same time.
8. The method of claim 1 , wherein
the cache memory comprises a plurality of sets and a plurality of ways;
the given request specifies a given set, but not which way;
the checking identifies a way; and
the result relates to the identification of the way.
9. The method of claim 1 , wherein checking comprises verifying that a line has not been evicted.
10. Within a cache memory control unit, apparatus comprising:
at least one input adapted to receive at least one memory access request;
at least one directory unit adapted to retrieve data from cache lines responsive to the memory access request; and
at least one storage unit adapted to retain an indication responsive to the memory access request, so that the indication can be used in a subsequent memory access request, wherein
said directory unit comprises conflict checking mechanisms relating to speculative execution in a processor coupled with the cache control unit, and said indication allowing the subsequent memory access to use data from the cache without repeating conflict checking.
11. The apparatus of claim 10 , wherein the indication comprises data related to contents of a cache line.
12. The apparatus of claim 10 , wherein the cache memory comprises a plurality of ways and the indication identifies at least one of the ways that was associated with the request.
13. The apparatus of claim 10 , wherein when the memory access request is associated with a line eviction from the cache, an invalidation of a previously established indication is issued.
14. A system comprising
at least one processor;
a cache memory shared by the at least one processor, comprising:
a directory unit, for retrieving data responsive to memory access requests from the processors lines for storing data; and
a register adapted to store at least one address or data result related to a prior memory access request, wherein
a plurality of processors are adapted to perform speculative execution in parallel;
said cache configured to manage conflict detection for the processors;
the register operating to avoid conflict detection for sequential requests to access a same memory resource.
15. The system of claim 14 , wherein the cache is adapted to reorder requests so that requests for the same memory resource are sequential.