Method for fabricating buried bit lines
A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.
1. A method for fabricating buried bit lines, comprising the steps of:
Step S 1 : defining a plurality of parallel masked regions and a plurality of first etched regions on a surface of a substrate, wherein each of the plurality of first etched regions is formed between any two neighboring masked regions, and wherein each of the plurality of masked regions is formed at a width greater than that of each of the plurality of first etched regions;
Step S 2 : etching the substrate where the plurality of first etched regions are formed to form a plurality of first trenches corresponding to the plurality of first etched regions and a plurality of first pillars corresponding to the plurality of masked regions;
Step S 3 : implanting first conductive ions into two sidewalls of each of the plurality of first trenches to form two bit lines respectively on two sidewalls of each of the plurality of first pillars;
Step S 4 : filling a packing material into the plurality of first trenches;
Step S 5 : respectively forming a plurality of second etched regions on the plurality of first pillars to parallel to the plurality of first etched regions without contacting the packing material; and
Step S 6 : etching the plurality of second etched regions to form a plurality of second trenches and a plurality of second pillars, and wherein the plurality of second pillars are corresponding to the bit lines.
2. The method for fabricating buried bit lines according to claim 1 , wherein a ratio of the widths of the masked region and the first etched regions is 3:1.
3. The method for fabricating buried bit lines according to claim 1 , wherein the substrate includes a semiconductor layer, a first isolation layer, an etching retard layer and a second isolation layer that are stacked in sequence.
4. The method for fabricating buried bit lines according to claim 3 , wherein the semiconductor layer is made of silicon; the first isolation layer and the second isolation layer are made of silicon nitride; the etching retard layer is made of silicon dioxide.
5. The method for fabricating buried bit lines according to claim 3 , wherein the Step S 5 further comprises the steps of
Step S 5 A: etching away the second isolation layer to allow the packing material to protrude from the etching retard layer;
Step S 5 B: depositing a blocking layer on surfaces of the etching retard layer and the packing material; and
Step S 5 C: performing an etch-back process on the blocking layer and the etching retard layer to form the plurality of second etched regions on a surface of the first isolation layer.
6. The method for fabricating buried bit lines according to claim 5 , wherein in the Step S 5 B, the blocking layer is deposited through an ALD (Atomic Layer Deposition) or MLD (Molecular Layer Deposition) technique.
7. The method for fabricating buried bit lines according to claim 1 , wherein the packing material is made of silicon dioxide.
8. The method for fabricating buried bit lines according to claim 1 , wherein the plurality of masked regions are formed by depositing a plurality of photoresist layers on the surface of the substrate.
9. The method for fabricating buried bit lines according to claim 1 further comprising Step S 7 after the Step S 6 : implanting second conductive ions into the second trenches where the bit lines are formed to allow the bit lines to include the first conductive ions and the second conductive ions.
10. The method for fabricating buried bit lines according to claim 9 , wherein the first conductive ions and the second conductive ions are made of an element of Group V.