Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage
A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
1. A semiconductor device comprising:
a substrate;
a well region formed in the substrate;
a first shallow trench isolation region formed on and adjacent to the well region, wherein the first shallow trench isolation region is proximate to a body contact doped with the dopants of a first polarity type;
a source region formed on the well region and adjacent to the first shallow trench isolation region;
a drift region formed in the substrate adjacent to the well region;
a second shallow trench isolation region formed on and adjacent to the drift region;
a drain region formed on the drift region and adjacent to the second shallow trench isolation region;
a gate formed between the source region and the drain region;
a sidewall spacer formed adjacent to sidewalls of the gate; and
a stress layer deposited over the semiconductor device, wherein the stress layer is also deposited inside the second shallow trench isolation region, and wherein the stress layer is proximate to the drift region.
2. The semiconductor device of claim 1 , wherein:
the semiconductor device is a lateral diffused metal-oxide-semiconductor field effect transistor;
the substrate is doped with dopants of the first polarity type.
3. The semiconductor device of claim 2 , wherein:
the well region is doped with the dopants of the first polarity type, and the well region further comprises the body contact; and
the source region, drift region, and drain region are doped with dopants of a second polarity type.
4. The semiconductor device of claim 3 , wherein the first shallow trench isolation region and the second shallow trench isolation region comprise dielectric material, which includes oxide, nitride, or any other dielectric material.
5. The semiconductor device of claim 4 , wherein a portion of the dielectric material in the second shallow trench isolation region is removed utilizing one or more processes which include anisotropic reactive ion etching (RIE), or any other practical etching method.
6. The semiconductor device of claim 5 , wherein the gate further comprises a gate dielectric layer, a metal layer, and a polycrystalline silicon (poly) layer.
7. The semiconductor device of claim 6 , wherein:
the stress layer is deposited utilizing plasma-enhanced chemical vapor deposition to provide stress of about 1 GPa; and
the stress layer comprises silicon nitride.
8. The semiconductor device of claim 7 , wherein a portion of the stress layer over the semiconductor device is removed to form an opening, which propagates stress of about 1 GPa into the region below the gate to enhance the flow of current through the semiconductor device.
9. The semiconductor device of claim 8 , wherein:
the gate dielectric and the sidewall spacer further comprise oxide, nitride, or any other dielectric material; and
contacts comprising silicide are formed on a portion of the drain region, gate, and source region.
10. The semiconductor device of claim 9 , wherein the dopants of the first polarity type for the well region and for the body contact are interchanged with the dopants of the second polarity type for the source region, drift region, and drain region.
11. The semiconductor device of claim 10 , wherein:
the drift region is formed on and adjacent to an n-band well region; and the n-band well region is formed in the substrate, which is doped with one of a group of n-type dopants that include phosphorus, arsenic, or antimony.