Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line and placed on both sides of the gate contact over a layer of insulating material. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars over an insulating material on the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.
1. A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate, the method comprising:
etching a gate contact region into the substrate;
depositing the insulating material into the gate contact region after etching the gate contact region;
etching the insulating material in the gate contact region to form the layer of insulating material;
forming a pair of pillars over the insulating material on the gate contact region of the substrate;
depositing an electrically conductive gate material between and over the pillars;
etching the gate material such that the gate material partially fills a space between the pair of pillars, the gate material forming a word line for the memory cells; and
depositing a gate contact between the pair of pillars such that the gate contact is in electrical contact with the gate material; and
wherein the memory cells are phase change memory cells.
2. The method as in claim 1 , wherein the memory cells include Ge2Sb2Te5.
3. The method as in claim 1 , wherein the memory cells include SbTe materials.
4. The method as in claim 1 , wherein the memory cells include In2Se3.
5. A method as in claim 1 , wherein the insulating material is silicon dioxide.
6. A method as in claim 1 , wherein the memory cells include vertical access transistors.
7. A method as in claim 1 , further comprising forming a bit line with a pitch at least one lithographic feature size less than the word line pitch.
8. A method as in claim 7 , further comprising:
forming a bit line with a pitch of two lithographic feature sizes; and
forming the word line with a pitch of three lithographic feature sizes.
9. A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate, the method comprising:
etching a gate contact region into the substrate;
depositing the insulating material into the gate contact region after etching the gate contact region;
etching the insulating material in the gate contact region to form the layer of insulating material;
forming a pair of pillars over the insulating material on the gate contact region of the substrate;
depositing an electrically conductive gate material between and over the pillars;
etching the gate material such that the gate material partially fills a space between the pair of pillars, the gate material forming a word line for the memory cells; and
depositing a gate contact between the pair of pillars such that the gate contact is in electrical contact with the gate material; and
forming a bit line with a pitch at least one lithographic feature size less than the word line pitch.
10. The method as in claim 9 , wherein the memory cells include Ge2Sb2Te5.
11. The method as in claim 9 , wherein the memory cells include SbTe materials.
12. The method as in claim 9 , wherein the memory cells include In2Se3.
13. The method as in claim 9 , wherein the insulating material is silicon dioxide.
14. The method as in claim 9 , wherein the memory cells include vertical access transistors.
15. The method as in claim 9 , further comprising:
forming a bit line with a pitch of two lithographic feature sizes; and
forming the word line with a pitch of three lithographic feature sizes.