Integrated circuit including DRAM and SRAM/logic
An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
1. An integrated circuit comprising field effect transistors (FETs) at least some of which comprise a part of random access memory (RAM) and logic devices, comprising:
an N+ type layer having a top surface;
a P type region formed in the N+ type layer;
an insulator layer having a top surface and a bottom surface, the bottom surface overlying the top surface of the N+ type layer;
a silicon layer overlying the top surface of the insulator layer;
an embedded dynamic RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor;
a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer;
a first logic/static RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic/static RAM FET; and
a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
2. The integrated circuit as in claim 1 , where the P type region is comprised of a P type layer having a thickness and disposed within the N+ type layer.
3. The integrated circuit as in claim 2 , further comprising a deep trench isolation structure extending through the silicon layer, the insulating layer and into the N+ type layer to a depth that is greater than a depth at which the P type layer is disposed, the deep trench isolation structure abutting an edge of the P type layer.
4. The integrated circuit as in claim 2 , further comprising an intrinsic layer disposed within the N+ type layer between the P type layer and the N+ type layer.
5. The integrated circuit as in claim 1 , further comprising:
an N or N+ type region formed in the P type region;
a second logic/static RAM FET formed in the silicon layer above the N or N+ type region, the N or N+ type region functional as an N-type back gate of the second logic/static RAM FET; and
a third contact through the silicon layer and the insulating layer and electrically connecting to the N or N+ type region.
6. The integrated circuit as in claim 5 , where the P type region is comprised of a P type layer having a thickness and disposed within the N+ type layer, where the N or N+type region is comprised of an N or N+ type layer having a thickness and disposed adjacent to the P type layer, where the bottom surface of the insulator layer overlies a top surface of the P type region and a top surface of the N or N+ type region; further comprising:
a first deep trench isolation structure extending through the silicon layer, the insulating layer and into the N+ type layer to a depth that is greater than a depth at which the P type layer is disposed, the first deep trench isolation structure abutting a first edge of the P type layer; and
and a second deep trench isolation structure extending through the silicon layer, the insulating layer and into the N+ type layer between the P type layer and the N or N+ type layer to a depth that is greater than a depth at which the P type layer and the N or N+ type layer are disposed, the second deep trench isolation structure abutting a second edge of the P type layer opposite the first edge and also abutting an edge of the N or N+ type layer.
7. The integrated circuit as in claim 6 , further comprising an intrinsic layer disposed within the N+ type layer between the P type region and the N+ type layer and between the N or N+ type region and the N+ layer.
8. The integrated circuit as in claim 1 , further comprising a second logic/static RAM FET formed in the silicon layer above the P type region, the P type region functional as a common P-type back gate of the first logic/static RAM FET and the second logic/static RAM FET.
9. The integrated circuit as in claim 8 , where one of the first and the second logic/static RAM FETs is an N-type FET, and where the other one of the first and the second logic/static RAM FETs is a P-type FET.
10. The integrated circuit as in claim 5 , where one of the first and the second logic/static RAM FETs is an N-type FET, where the other one of the first and the second logic/static RAM FETs is a P-type FET.
11. The integrated circuit as in claim 5 , where during operation the first contact, the second contact and the third contact are coupled to a same bias voltage potential, or where at least one of the first contact, the second contact and the third contact is coupled to a first bias voltage potential and at least one other one of the first contact, the second contact and the third contact is coupled to a second bias potential that differs from the first bias potential.
12. An integrated circuit comprising field effect transistors (FETs) at least some of which comprise a part of random access memory (RAM) and logic devices, comprising:
an N+ type layer;
a P type region formed in the N+ type layer;
an insulator layer overlying the N+ type layer;
a silicon layer overlying the insulator layer;
an embedded dynamic RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor;
a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer;
a first logic/static RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic/static RAM FET;
a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region;
an N or N+ type region formed in the P type region;
a second logic/static RAM FET formed in the silicon layer above the N or N+ type region, the N or N+ type region functional as an N-type back gate of the second logic/static RAM FET; and
a third contact through the silicon layer and the insulating layer and electrically connecting to the N or N+ type region, where
the P type region is comprised of a P type layer having a thickness and disposed within the N+ type layer, where the N or N+ type region is comprised of an N or N+ type layer having a thickness and disposed adjacent to the P type layer; further comprising:
a first deep trench isolation structure extending through the silicon layer, the insulating layer and into the N+ type layer to a depth that is greater than a depth at which the P type layer is disposed, the first deep trench isolation structure abutting a first edge of the P type layer; and
and a second deep trench isolation structure extending through the silicon layer, the insulating layer and into the N+ type layer between the P type layer and the N or N+ type layer to a depth that is greater than a depth at which the P type layer and the N or N+ type layer are disposed, the second deep trench isolation structure abutting a second edge of the P type layer opposite the first edge and also abutting an edge of the N or N+ type layer.
13. The integrated circuit as in claim 12 , further comprising an intrinsic layer disposed within the N+ type layer between the P type region and the N+ type layer and between the N or N+ type region and the N+ layer.
14. The integrated circuit as in claim 12 , further comprising another logic/static RAM FET formed in the silicon layer above the P type region, the P type region functional as a common P-type back gate of the first logic/static RAM FET and the another logic/static RAM FET.
15. The integrated circuit as in claim 14 , where one of the first and the second logic/static RAM FETs is an N-type FET, and where the other one of the first and the second logic/static RAM FETs is a P-type FET.
16. The integrated circuit as in claim 12 , where during operation the first contact, the second contact and the third contact are coupled to a same bias voltage potential, or where at least one of the first contact, the second contact and the third contact is coupled to a first bias voltage potential and at least one other one of the first contact, the second contact and the third contact is coupled to a second bias potential that differs from the first bias potential.
17. The integrated circuit as in claim 12 , where the silicon layer is a silicon-on-insulator (SOI) layer and where the insulator layer is a buried oxide (BOX) layer.