Method for forming pad in wafer with three-dimensional stacking structure
A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
1. A method for forming a pad in a wafer with a three-dimensional stacking structure, comprising:
bonding a device wafer and a handling wafer, wherein the device wafer comprises an Si substrate;
thinning a back side of the Si substrate;
depositing an anti-reflective layer on the thinned back side of the Si substrate;
depositing a back side dielectric layer on the anti-reflective layer;
defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, wherein the defining a space for the pad and forming the vias are performed by a photolithographic process;
filling one or more metals in the vias and the defined space for the pad; and
removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
2. The method according to claim 1 , wherein the vias are filled with tungsten (W).
3. The method according to claim 2 , wherein filling of tungsten is implemented through electro/electroless plating.
4. The method according to claim 1 , wherein the defined space for the pad is filled with copper (Cu) or aluminum (Al).
5. The method according to claim 4 , wherein filling of copper or aluminum is implemented through electro/electroless plating.
6. The method according to claim 2 , wherein the defined space for the pad is filled with copper (Cu) or aluminum (Al).
7. The method according to claim 1 , wherein the vias and the pad are formed by a dual damascene process.
8. The method according to claim 1 , wherein the anti-reflective layer comprises oxynitride.
9. The method according to claim 1 , wherein the anti-reflective layer is deposited to a thickness of equal to or less than 500 Å.
10. The method according to claim 1 , wherein the back side dielectric layer is deposited to a thickness of 1,000 Åto 5,000 Å.
11. The method according to claim 1 , wherein the thinned Si substrate has a thickness of 2 μm to 6 μm.
12. The method according to claim 11 , wherein the thinned Si substrate has a thickness of about 3 μm.
13. The method according to claim 1 , further comprising forming optical filters for transmitting light of a specified band on the back side of the back side dielectric layer.
14. The method according to claim 13 , further comprising forming microlenses for focusing light on the optical filters.