Diode structure and method for wire-last nanomesh technologies
In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
1. A method of fabricating an electronic device, comprising:
providing a semiconductor-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX);
forming an alternating series of device layers and sacrificial layers in a stack on the wafer, wherein one or more of the sacrificial layers are doped with a dopant;
etching nanowire bars into the device layers and sacrificial layers in at least one first portion and in at least one second portion of the stack such that each of the device layers in the at least one first portion of the stack and each of the device layers in the at least one second portion of the stack has a source region, a drain region and nanowire channels connecting the source region and the drain region;
diffusing the dopant from the sacrificial layers into the source region and the drain region of each of the device layers in the at least one first portion of the stack and into the source region, the drain region and the nanowire channels of each of the device layers in the at least one second portion of the stack;
removing the sacrificial layers from between the nanowire bars;
selectively forming a conformal gate dielectric layer surrounding the nanowire channels in the at least one first portion of the stack which serve as a channel region of a nanomesh field-effect transistor (FET) transistor;
forming a first gate on the conformal gate dielectric layer surrounding the nanowire channels in the at least one first portion of the stack which serve as the channel region of the nanomesh FET transistor in a gate all around configuration; and
forming a second gate surrounding the nanowire channels in the at least one second portion of the stack which serve as a channel region of a nanomesh FET-diode in another gate all around configuration.
2. The method of claim 1 , further comprising:
isolating the at least one first portion of the stack from the at least one second portion of the stack using shallow trench isolation.
3. The method of claim 1 , further comprising:
selectively removing the sacrificial layers from between the nanowire bars in the at least one first portion of the stack prior to the diffusing.
4. The method of claim 3 , further comprising:
forming a resist mask covering the at least one second portion of the stack so as to permit selective removal of the sacrificial layers from between the nanowire bars in the at least one first portion of the stack.
5. The method of claim 3 , further comprising:
removing the sacrificial layers from between the nanowire bars in the at least one second portion of the stack after the diffusing has been performed.
6. The method of claim 1 , wherein the selectively forming the conformal gate dielectric layer surrounding the nanowire channels in the at least one first portion of the stack comprises:
depositing the conformal gate dielectric layer surrounding i) the nanowire channels in the at least one first portion of the stack and ii) the nanowire channels in the at least one second portion of the stack; and
selectively removing the conformal gate dielectric from the nanowire channels in the at least one second portion of the stack.
7. The method of claim 6 , further comprising:
forming a resist mask covering the at least one first portion of the stack so as to permit selective removal of the conformal gate dielectric from the nanowire channels in the at least one second portion of the stack.
8. The method of claim 1 , wherein the conformal gate dielectric layer comprises a high-k material.