Active matrix using hybrid integrated circuit and bipolar transistor
A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
1. A hybrid integrated circuit device, comprising:
a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness;
first devices formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer;
second devices formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side; and
at least one through via connection configured to connect the first metallizations to the second metallizations through the dielectric layer.
2. The device as recited in claim 1 , wherein the first devices include complementary metal oxide semiconductor devices and the second devices include at least one of a bipolar transistor and a junction field effect transistor.
3. The device as recited in claim 1 , wherein the base substrate includes a single crystal or multi-crystal material, and the second devices include transistors employing the base substrate as a transistor body.
4. The device as recited in claim 1 , wherein at least one of the first devices and the second devices are included in an active matrix display.
5. The device as recited in claim 1 , wherein the base substrate layer includes doped regions formed therein and the doped regions connect to the at least one through via connection to connect the first metallizations to the second metallizations.
6. The device as recited in claim 1 , wherein the first metallizations are connected to the second metallizations by metal-to-metal contact including the at least one through via connection.
7. The device as recited in claim 1 , wherein the second devices include a bipolar transistor formed in a single crystal or multi-crystal base material and having doped regions formed from hydrogenated silicon patterned on the base material; wherein the hydrogenated Si includes 5-40 atomic percent hydrogen.
8. A pixel circuit for an active matrix display, comprising:
a junction field effect transistor (JFET) enabled by a select signal;
a bipolar junction coupled to the JFET to receive data through the JFET, when enabled, at a base of the bipolar junction, the JFET and the bipolar junction including a crystalline channel material; and
an organic light emitting diode (OLED) being connected on one side between one of an emitter and a collector of the bipolar junction and, on the other side, between one of supply voltage and ground,
wherein the circuit is a direct programming circuit and the OLED includes a bottom-emission device.
9. The circuit as recited in claim 8 , wherein the JFET includes an n-type channel material and the bipolar junction includes a p-n-p junction such that current through the OLED includes: I OLED ≈β(V dd −V data −V EB )/R ON where β is a ratio of collector current to base current, V dd is a supply voltage, V data is a data voltage, V EB is emitter-base voltage and R ON is an on resistance of the JFET.
10. The circuit as recited in claim 8 , wherein the JFET includes a p-type channel material and the bipolar junction includes a n-p-n junction such that current through the OLED includes: I OLED ≈β(V data −V BE −V OLED )/R ON where β is a ratio of collector current to base current, V data is a data voltage, V BE is base-emitter voltage, V OLED is a voltage across the OLED and R ON is an on resistance of the JFET.
11. The circuit as recited in claim 8 , further comprising a storage capacitor coupled between a base of the bipolar junction and between one of supply voltage and ground.
12. The circuit as recited in claim 8 , being formed on a hybrid integrated circuit device, comprising:
a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness;
first devices formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer;
second devices including the pixel circuit formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side; and
at least one through via connection configured to connect the first metallizations to the second metallizations through the dielectric layer.
13. The circuit as recited in claim 12 , wherein the first devices include complementary metal oxide semiconductor devices.
14. The circuit as recited in claim 12 , wherein the base substrate includes a single crystal or multi-crystal material, and the second devices include transistors employing the base substrate as a transistor body.
15. The circuit as recited in claim 12 , wherein at least one of the first devices and the second devices are included in an active matrix display.
16. The circuit as recited in claim 12 , wherein the base substrate layer includes doped regions formed therein and the doped regions connect to the at least one through via connection to connect the first metallizations to the second metallizations.
17. The circuit as recited in claim 12 , wherein the first metallizations are connected to the second metallizations by metal-to-metal contact including the at least one through via connection.
18. The circuit as recited in claim 12 , wherein the second devices include bipolar transistors formed in a single crystal or multi-crystal base material and having doped regions formed from amorphous silicon patterned on the base material.
19. A pixel circuit for an active matrix display, comprising:
a junction field effect transistor (JFET) enabled by a select signal;
a bipolar junction coupled to the JFET to receive data through the JFET, when enabled, at a base of the bipolar junction, the JFET and the bipolar junction including a crystalline channel material; and
an organic light emitting diode (OLED) being connected on one side between one of an emitter and a collector of the bipolar junction and, on the other side, between one of supply voltage and ground,
wherein the circuit is a non-direct programming circuit and the OLED includes a top-emission device.
20. The circuit as recited in claim 19 , wherein the JFET includes an n-type channel material and the bipolar junction includes a p-n-p junction such that current through the OLED includes: I OLED ≈β(V dd −V data −V EB )/R ON where β is a ratio of collector current to base current, V dd is a supply voltage, V data is a data voltage, V EB is emitter-base voltage and R ON is an on resistance of the JFET.
21. The circuit as recited in claim 19 , wherein the JFET includes a p-type channel material and the bipolar junction includes a n-p-n junction such that current through the OLED includes: I OLED ≈β(V data −V BE −V OLED )/R ON where β is a ratio of collector current to base current, V data is a data voltage, V BE is base-emitter voltage, V OLED is a voltage across the OLED and R ON is an on resistance of the JFET.
22. The circuit as recited in claim 19 , further comprising a storage capacitor coupled between a base of the bipolar junction and between one of supply voltage and ground.
23. The circuit as recited in claim 19 , being formed on a hybrid integrated circuit device, comprising:
a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness;
first devices formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer;
second devices including the pixel circuit formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side; and
at least one through via connection configured to connect the first metallizations to the second metallizations through the dielectric layer.
24. The circuit as recited in claim 23 , wherein the first devices include complementary metal oxide semiconductor devices.
25. The circuit as recited in claim 23 , wherein the base substrate includes a single crystal or multi-crystal material, and the second devices include transistors employing the base substrate as a transistor body.
26. The circuit as recited in claim 23 , wherein the base substrate layer includes doped regions formed therein and the doped regions connect to the at least one through via connection to connect the first metallizations to the second metallizations.
27. The circuit as recited in claim 23 , wherein the first metallizations are connected to the second metallizations by metal-to-metal contact including the at least one through via connection.
28. The circuit as recited in claim 23 , wherein the second devices include bipolar transistors formed in a single crystal or multi-crystal base material and having doped regions formed from amorphous silicon patterned on the base material.