FET semiconductor device with low resistance and enhanced metal fill
In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of substrate. The dummy gate is removed and the height of the gate channel is reduced to substantially near that of a top surface of one or more FINs. A layer of high-k material is deposited into the gate channel. A layer of first metal is then deposited that fills the gate channel and covers, at least in part, the layer of high-k material. Excess material is removed from the layers of high-k material and first metal to create a surface. A layer of second metal is selectively deposited onto the surface to form a continued gate conductor.
1. A method of fabricating a FET semiconductor device, the method comprising:
forming a structure on top of a substrate, the structure including a gate channel that perpendicularly crosses over one or more FINs and is filled with a dummy gate material; and spacer layers that line, at least in part, sidewalls of the gate channel and abut the substrate, the spacer layers having a height from the substrate to a distal end of the spacer layer, the gate channel having a height being the same as that of the spacer layers;
removing the dummy gate material;
reducing the height of the gate channel to substantially near a top surface of the one or more FINs inside the gate channel;
depositing a layer of high-k material into the gate channel;
depositing a layer of first metal into the gate channel, wherein the layer of first metal covers, at least in part, the layer of high-k material, and the layer of first metal fills the gate channel;
removing excess material of said high-k material and said first metal to create a surface having a height substantially the same as that of said spacer layers; and
selectively depositing a layer of second metal on top of said surface directly onto a remaining portion of said first metal, wherein the layer of second metal and the layer of first metal form a continued gate conductor with a high aspect ratio.
2. The method of claim 1 , wherein the layer of first metal fills the gate channel substantially to the height of the spacer layers.
3. The method of claim 1 , wherein the FET device further includes a layer which includes a source and a drain that are covered by a layer of inter layer dielectric, the gate channel being located between the source and the drain.
4. The method of claim 3 , wherein a height of the layer of inter layer dielectric is substantially the same as the height of the gate channel.
5. The method of claim 3 , wherein the layer which includes the source and the drain constitutes a merged source and drain epitaxial layer.
6. The method of claim 4 , the method further including:
reducing the height of the layer of inter layer dielectric to be substantially the same as the height of the spacer layers.
7. The method of claim 1 , wherein the step of reducing the height of the gate channel to substantially near the one or more FINs included in the gate channel includes reducing the height of the spacer layers.
8. The method of claim 1 , the method further including the step of:
depositing, following the step of depositing the layer of high-k material, a layer of work-function material on top of the layer of high-k material.
9. The method of claim 8 , wherein the work-function material includes at least one selected from a group consisting of TiN, TiAl, TiAlN, TiAlNC, TaAlNC, HfSi, La, TaN, Ru, and Cu.
10. The method of claim 1 , wherein the high-k material includes at least one selected from a group consisting of hafnium oxide (HfO 2 ), hafnium silicates (HfSiOx), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 3 ), and lanthanum oxide (La 2 O 3 ).
11. The method of claim 1 , wherein one or both of the layer of first metal and the layer of second metal include at least one selected from a group consisting of silver, copper, gold, aluminum, calcium, tungsten, and zinc.
12. A method of fabricating a FET semiconductor device, the method comprising:
forming a structure on top of a substrate, the structure including a gate channel that includes one or more FINs and is filled with a dummy gate material; at least one spacer layer that lines at least one sidewall of the gate channel and abuts the substrate, the spacer layer having a height measured from the substrate to a distal end of the spacer layer, wherein the height of the spacer layer is substantially equal to a height of the gate channel;
removing the dummy gate material;
reducing the height of the gate channel to substantially near a top surface of the one or more FINs included in the gate channel;
lining the gate channel with a layer of high-k material;
lining the gate channel with a layer of first metal, the layer of first metal covering the layer of high-k material and fills the gate channel;
removing excess material from the layer of first metal to create a surface; and
selectively depositing a layer of second metal on top of the surface, wherein the layer of second metal and the layer of first metal form a continued gate conductor with a high aspect ratio.
13. The method of claim 12 , wherein the layer of first metal fills the gate channel substantially to the height of the spacer layers.
14. The method of claim 12 , wherein the FET device further includes a merged source and drain epitaxial layer that is covered by a layer of inter layer dielectric.
15. The method of claim 1 , the method further including the step of:
lining the gate channel, following the step of lining the gate channel with a layer of high-k material, with a layer of work-function material.