Three-dimensional NAND non-volatile memory devices with buried word line selectors
Three-dimensional NAND stacked memory devices include a stack including alternating word line and dielectric layers and a plurality of NAND strings of memory cells formed in memory holes which extend through the layers. Each memory cell includes a control gate formed by one of the word line layers, and multiple selector devices, each selector device coupled to an end of a corresponding NAND string. The NAND strings are disposed above a substrate, and the selector devices are disposed in the substrate.
1. A three-dimensional stacked non-volatile memory device comprising:
a stack comprising alternating word line and dielectric layers and a plurality of NAND strings of memory cells formed in memory holes which extend through the layers, each memory cell comprising a control gate formed by one of the word line layers; and
a plurality of selector devices, each selector device coupled to an end of a corresponding NAND string,
wherein the NAND strings are disposed above a substrate, and the selector devices are disposed in the substrate.
2. The three-dimensional stacked non-volatile memory device of claim 1 , wherein each selector device comprises a buried word line.
3. The three-dimensional stacked non-volatile memory device of claim 2 , wherein each buried word line is disposed in a corresponding trench in the substrate.
4. The three-dimensional stacked non-volatile memory device of claim 1 , further comprising a plurality of select gate transistors, each select gate transistor comprising a corresponding one of the selector devices.
5. The three-dimensional stacked non-volatile memory device of claim 4 , wherein each select gate transistor comprises a source-side select gate transistor or a drain-side select gate transistor.
6. The three-dimensional stacked non-volatile memory device of claim 1 , further comprising a plurality of source lines, wherein each selector device is coupled to a corresponding one of the source lines.
7. The three-dimensional stacked non-volatile memory device of claim 6 , wherein the source lines each comprise a multi-layer stack of a non-conductive material layer, a first conductive material layer, and a second conductive material layer.
8. The three-dimensional stacked non-volatile memory device of claim 1 , further comprising a plurality of bit lines, wherein each selector device is coupled to a corresponding one of the bit lines.
9. The three-dimensional stacked non-volatile memory device of claim 8 , wherein the bit lines each comprise a multi-layer stack of a non-conductive material layer, a first conductive material layer, and a second conductive material layer.