SCR with fin body regions for ESD protection
An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
1. A method of manufacturing a semiconductor structure, comprising:
forming a semiconductor controlled rectifier comprising a first plurality of fingers of semiconductor material between an n-well body contact and an anode in an n-well, and a second plurality of fingers of semiconductor material between a p-well body contact and a cathode in a p-well,
wherein the semiconductor controlled rectifier comprises: a first dielectric structure on and between ones of the first plurality of fingers of semiconductor material; and a second dielectric structure on and between ones of the second plurality of fingers of semiconductor material.
2. The method of claim 1 , wherein:
the first dielectric structure comprises a first gate stack; and
the second dielectric structure comprises a second gate stack.
3. The method of claim 2 , wherein:
the first gate stack includes a first gate dielectric, a first non-conductive gate body, and first sidewall spacers; and
the second gate stack includes a second gate dielectric, a second non-conductive gate body, and second sidewall spacers.
4. The method of claim 1 , wherein the first dielectric structure directly contacts: each of the first plurality of fingers of semiconductor material; a buried oxide layer; the n-well body contact; and the anode.
5. The method of claim 1 , wherein:
a first one of the first plurality of fingers of semiconductor material has a first end directly contacting the n-well body contact and a second end directly contacting the anode; and
a second one of the first plurality of fingers of semiconductor material has a first end directly contacting the n-well body contact and a second end directly contacting the n-well.
6. The method of claim 1 , wherein each of the second plurality of fingers of semiconductor material has respective ends directly contacting the p-well without directly contacting the cathode or the p-well body contact.
7. The method of claim 1 , wherein each of the second plurality of fingers of semiconductor material is composed of intrinsic polysilicon.
8. The method of claim 7 , wherein the intrinsic polysilicon is different than a material of the p-well.
9. A method of manufacturing a semiconductor structure, comprising:
forming a semiconductor controlled rectifier comprising a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well, wherein the forming the semiconductor controlled rectifier comprises:
forming a plurality of fins;
forming a first dielectric structure on and between ones of the plurality of fins;
forming a second dielectric structure on and between the ones of the plurality of fins;
forming a semiconductor material layer by merging the plurality of fins where the plurality of fins are uncovered by the first dielectric structure and the second dielectric structure;
forming the n-well, the n-well body contact, and the anode in a first region of the semiconductor material layer; and
forming the p-well, the p-well body contact, and the cathode in a second region of the semiconductor material layer.
10. The method of claim 9 , wherein:
the first plurality of fingers comprises first portions of the plurality of fins covered by the first dielectric structure and between the n-well body contact and the anode; and
the second plurality of fingers comprises second portions of the plurality of fins covered by the second dielectric structure and between the p-well body contact and the cathode.
11. The method of claim 10 , further comprising doping the first plurality of fingers a same conductivity type as the n-well.
12. The method of claim 9 , wherein:
the forming the first dielectric structure comprises forming a first gate stack at a first location on and between the ones of the plurality of fins; and
the forming the second dielectric structure comprises forming a second gate stack at a second location on and between the ones of the plurality of fins.
13. The method of claim 9 , wherein:
the forming the first dielectric structure comprises forming a first hard mask at a first location on and between the ones of the plurality of fins; and
the forming the second dielectric structure comprises forming a second hard mask at a second location on and between the ones of the plurality of fins.
14. The method of claim 9 , wherein the merging the plurality of fins comprises epitaxially growing semiconductor material on the plurality of fins.
15. The method of claim 9 , further comprising:
forming a blocking spacer on an upper surface of the semiconductor material layer; and
increasing a thickness of the semiconductor material layer in regions that are uncovered by the blocking spacer.
16. The method of claim 15 , wherein the forming the blocking spacer comprises forming the blocking spacer over junction regions of the semiconductor controlled rectifier.