Frequency locking oscillator
A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.
1. A method performed by a system comprising a delay line, the delay line comprising a plurality of delay elements connected in a cascade from a first delay element to a last delay element, the method comprising:
receiving an input clock signal at an input to the delay line, the input clock signal having a period;
configuring a plurality of selecting elements to define a delay path through the delay elements, the delay path having a total delay based on the period of the input clock signal, wherein:
each delay element after the first delay element is configured to time delay the input clock signal by a time period that is a multiple of the time period of the prior delay element in the cascade; and
the first delay element is configured to delay the input clock signal by a minimum time delay longer than a time delay between a delay select register configured to select between the selecting elements and the outputs of the selecting elements, the delay select register being configured to store a value indicative of the total delay of the delay path and output control signals to the plurality of selecting elements based on the stored value, the stored value being adjusted based on a frequency of an output signal of the delay line; and
for a given number of clock cycles of the input clock signal, incrementing a first counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal of the delay line arrives at the counting circuit, the counting circuit comprising two or more flip-flops, each of the two or more flip-flops being clocked by the input clock signal.
2. The method of claim 1 , wherein the total delay of the delay path is one period of the input clock signal, and incrementing the first counter comprises incrementing the first counter if a positive edge of the input clock signal arrives at the counting circuit and a positive edge of the output signal arrives at the counting circuit.
3. The method of claim 1 , wherein the total delay of the delay path is high time of one period of the input clock signal, and the incrementing the first counter comprises incrementing the first counter if a negative edge of the input clock signal arrives at the counting circuit and a negative edge of the output signal arrives at the counting circuit.
4. The method of claim 1 , further comprising:
configuring the selecting elements to increase the total delay of the delay path from an initial setting;
for the same number of clock cycles, incrementing a second counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal arrives at the counting circuit;
configuring the selecting elements to decrease the total delay of the delay path from the initial setting; and
for the same number of clock cycles, incrementing a third counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal arrives at the counting circuit.
5. The method of claim 4 , further comprising building a histogram using the first, second, and third counters.
6. The method of claim 1 , wherein the counting circuit comprises: a first flip-flop coupled to the input clock signal and the output signal; logic coupled to an output of the first flip-flop; and a second flip-flop directly coupled to the input clock signal and an output of the logic, wherein an output of the second flip-flop is coupled to the logic.
7. The method of claim 1 , wherein each delay element comprises a standard cell selected from a library of standard cells.
8. A system comprising:
a delay line comprising a plurality of delay elements connected in a cascade from a first delay element to a last delay element; and
a plurality of selecting elements coupled to the delay line;
wherein the system is configured to perform operations comprising:
receiving an input clock signal at an input to the delay line, the input clock signal having a period;
configuring the selecting elements to define a delay path through the delay elements, the delay path having a total delay based on the period of the input clock signal, wherein:
each delay element after the first delay element is configured to time delay the input clock signal by a time period that is a multiple of the time period of the prior delay element in the cascade; and
the first delay element is configured to delay the input clock signal by a minimum time delay longer than a time delay between a delay select register configured to select between the selecting elements and the outputs of the selecting elements, the delay select register being configured to store a value indicative of the total delay of the delay path and output control signals to the plurality of selecting elements based on the stored value, the stored value being adjusted based on a frequency of an output signal of the delay line; and
for a given number of clock cycles of the input clock signal, incrementing a first counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal of the delay line arrives at the counting circuit, the counting circuit comprising two or more flip-flops, each of the two or more flip-flops being clocked by the input clock signal.
9. The system of claim 8 , wherein the total delay of the delay path is one period of the input clock signal, and incrementing the first counter comprises incrementing the first counter if a positive edge of the input clock signal arrives at the counting circuit and a positive edge of the output signal arrives at the counting circuit.
10. The system of claim 8 , wherein the total delay of the delay path is high time of one period of the input clock signal, and the incrementing the first counter comprises incrementing the first counter if a negative edge of the input clock signal arrives at the counting circuit and a negative edge of the output signal arrives at the counting circuit.
11. The system of claim 8 , the operations further comprising:
configuring the selecting elements to increase the total delay of the delay path from an initial setting;
for the same number of clock cycles, incrementing a second counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal arrives at the counting circuit;
configuring the selecting elements to decrease the total delay of the delay path from the initial setting; and
for the same number of clock cycles, incrementing a third counter if an edge of the input clock signal arrives at a counting circuit and an edge of the output signal arrives at the counting circuit.
12. The system of claim 11 , the operations further comprising building a histogram using the first, second, and third counters.
13. The system of claim 8 , wherein the counting circuit comprises: a first flip-flop coupled to the input clock signal and the output signal; logic coupled to an output of the first flip-flop; and a second flip-flop directly coupled to the input clock signal and an output of the logic, wherein an output of the second flip-flop is coupled to the logic.
14. The system of claim 8 , wherein each delay element comprises a standard cell selected from a library of standard cells.
15. The method of claim 1 , wherein the first delay element is not selectable.
16. The system of claim 8 , wherein the first delay element is not selectable.
17. The method of claim 1 , further comprising:
receiving a tuner ratio value and a reference clock signal; and
determining a difference between the frequency of the output signal divided by the tuner ratio value and the frequency of the reference clock signal,
wherein the stored value is adjustable based on the difference.
18. The method of claim 17 , wherein the stored value is increased if the frequency of the output signal divided by the tuner ratio value exceeds the frequency of the reference clock signal, and
wherein the stored value is decreased if the frequency of the output signal divided by the tuner ratio value is less than the frequency of the reference clock signal.
19. The system of claim 8 , wherein the stored value is adjusted based on a difference between the frequency of the output signal divided by a tuner ratio value and a frequency of the reference clock signal.
20. The system of claim 19 , wherein the stored value is increased if the frequency of the output signal divided by the tuner ratio value exceeds the frequency of the reference clock signal, and
wherein the stored value is decreased if the frequency of the output signal divided by the tuner ratio value is less than the frequency of the reference clock signal.