Formation of finFET junction

1. A method for forming a finFET comprising:

forming a dummy gate over a fin in a gate region of the finFET, wherein the dummy gate comprises a dummy dielectric layer in direct contact with the fin and a dummy material above the dummy dielectric layer;

forming a gate spacer pair over the fin sandwiching the dummy gate, wherein the gate spacer pair is located above the fin in an intermediate region of the finFET, and wherein the intermediate region of the finFET is adjacent to the gate region of the finFET;

forming a dummy spacer pair adjacent to the gate spacer pair, wherein the dummy spacer pair sandwiches the dummy gate and the gate spacer pair, and wherein the dummy spacer pair is located above the fin in the intermediate region of the finFET;

forming an epi-layer above the fin in a source/drain region of the finFET, wherein the epi-layer is in direct contact with the dummy spacer pair and the source/drain region is adjacent to the intermediate region of the finFET;

removing at least the dummy material to form a gate void;

forming a replacement gate in the gate void, wherein forming the replacement gate comprises depositing a dielectric layer in the gate void and then depositing an electrode in the gate void;

removing the dummy spacer pair after forming the replacement gate to form an implantation void;

implanting at least one dopant through the implantation void and into the fin located in the intermediate region of the finFET;

filling the implantation void with an insulating material to form an insulating layer; and

activating the at least one dopant in the fin located in the intermediate region of the finFET.

2. The method of claim 1 , wherein the implanted dopant comprises phosphorus, arsenic, boron or combinations thereof.

3. The method of claim 1 , wherein activating the dopant comprises applying a millisecond flash anneal or a laser spike anneal to the fin located in the intermediate region of the finFET.

4. The method of claim 1 , wherein the material forming the dummy spacer pair comprises a silicon nitride, a silicon oxide, or a silicon oxynitrides.

5. The method of claim 1 , wherein the material forming the gate spacer pair comprises a silicon nitride, a silicon oxide, or a silicon oxynitrides.

6. The method of claim 1 , wherein following activation the region of the fin located in the intermediate region of the finFET contains a first concentration of dopant and the region of the fin located in the gate region of the finFET contains a second concentration of dopant, and wherein there is at least an order of magnitude difference between the first concentration of dopant and the second concentration of dopant.

7. The method of claim 6 , wherein the distance between the first concentration of dopant and the second concentration of dopant is less than about 5 nm.

8. The method of claim 6 , wherein the second concentration of dopant is less than about 1×10 18 atoms/cm 3 .

9. A method for forming a finFET comprising:

forming a fin on a semiconductor substrate, wherein a portion of the fin is located in a gate region of the finFET, a portion of the fin is located in an intermediate region of the finFET and a portion of the fin is located in a source/drain region of the finFET and wherein the intermediate region of the finFET is between the gate region of the finFET and the source/drain region of the finFET;

forming a gate, wherein forming the gate comprises forming a gate dielectric above the portion of the fin located in the gate region of the finFET and then forming a gate electrode above the gate dielectric;

forming a dummy spacer pair over the portion of the fin located in the intermediate region of the finFET, wherein the dummy spacer pair sandwiches the gate;

forming an epi-layer above the portion of the fin located in the source/drain region of the finFET, wherein the epi-layer is in direct contact with the fin and the dummy spacer;

removing the dummy spacer pair to create an implantation void;

implanting at least one dopant through the implantation void and into the portion of the fin located in the intermediate region of the finFET; and

activating the at least one dopant in portion of the fin located in the intermediate region of the finFET.

10. The method of claim 9 , wherein the implanted dopants comprise phosphorus, arsenic, boron or combinations thereof.

11. The method of claim 9 , wherein activating the dopant comprises applying a millisecond flash anneal or a laser spike anneal to the portion of the fin located in the intermediate region of the finFET.

12. The method of claim 1 , wherein the material forming the dummy spacer pair comprises a silicon nitride, a silicon oxide, or a silicon oxynitrides.

13. The method of claim 1 , wherein the material forming the gate spacer pair comprises a silicon nitride, a silicon oxide, or a silicon oxynitrides.

14. The method of claim 9 , wherein following activation the portion of the fin located in the intermediate region of the finFET contains a first concentration of dopant and the portion of the fin located in the gate region of the finFET contains a second concentration of dopant, and wherein there is at least an order of magnitude difference between the first concentration of dopant and the second concentration of dopant.

15. The method of claim 14 , wherein the distance between the first concentration of dopant and the second concentration of dopant is less than about 5 nm.

16. The method of claim 14 , wherein the second concentration of dopant is less than about 1×10 18 atoms/cm 3 .