IP Library › Granted Patent US 9,515,085
Granted Patent B2
US 9,515,085 · App. 14/498,033 · Granted Dec 6, 2016

Vertical memory device with bit line air gap

Inventors: Peter Rabkin (Cupertino, CA); Jilin Xia (Milpitas, CA); Jayavel Pachamuthu (San Jose, CA)
Assignee: SANDISK TECHNOLOGIES LLC
H01L27/11582H01L21/02381H01L21/7682H01L21/76802H01L21/76877H01L23/528H01L27/1157H01L27/11524H01L27/11556
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Quick Facts
Patent No.
US 9,515,085
App. No.
14/498,033
Granted
Dec 6, 2016
Kind
B2
Abstract

A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.

Claims (19)

1. A monolithic three dimensional NAND string, comprising:

a plurality of semiconductor channels, at least one end portion of each semiconductor channel extending substantially perpendicular to a top surface of a substrate;

a plurality of drain regions, wherein each drain region contacts a top end of a respective one of the plurality of semiconductor channels;

a plurality of control gate electrodes extending substantially parallel to a top surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

a plurality of interlevel insulator layers located between the plurality of control gate electrodes, such that a first interlevel insulator layer is located between the first control gate electrode and the second control gate electrode;

a blocking dielectric located in contact with the plurality of control gate electrodes;

at least one charge storage region located in contact with the blocking dielectric;

a tunnel dielectric located between the at least one charge storage region and the semiconductor channel;

a plurality of bit lines; and

a plurality of electrical contacts, wherein each physically contacts a top surface of a respective one of the plurality of drain regions and is electrically connected to a respective one of the plurality of bit lines;

wherein a cavity or a low-k dielectric layer having a dielectric constant below 3.9 is located among the plurality of electrical contacts and above a horizontal plane including the top surfaces of the drain regions;

wherein: each of the plurality of electrical contacts comprises a lower contact pillar portion which contacts the respective one of the plurality of drain regions and an upper via contact portion which contacts a respective one of the plurality of bit lines; and

the lower contact pillar portion has a larger width or diameter than the upper via contact portion; and

wherein the cavity which comprises an air gap is located between the plurality of electrical contacts.

2. The NAND string of claim 1 , wherein the lower contact pillar portion comprises a cylindrical or inverted frustum shaped pillar, and the upper via contact portion comprises a cylindrical or inverted truncated cone shaped pillar which has a smaller average diameter than the contact pillar.

3. The NAND string of claim 1 , wherein the upper via contact portion has a first lateral dimension along a first horizontal direction that is parallel to an overlying bit line, and has a second lateral dimension along a second horizontal direction that that is perpendicular to the overlying bit line, the first lateral dimension being greater than the second lateral dimension.

4. The NAND string of claim 1 , wherein a horizontal cross section of the upper via contact portion has a first eccentricity which is greater than an eccentricity of a horizontal cross section of the lower contact pillar portion.

5. The NAND string of claim 1 , wherein the low-k dielectric layer having a dielectric constant below 3.9 is located between the plurality of electrical contacts.

6. The NAND string of claim 1 , wherein each of the plurality of electrical contacts has a substantially cylindrical shape or an inverted frustum shape.

Assignments (5)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0807 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2014
From: RABKIN, PETER; XIA, JILIN; PACHAMUTHU, JAYAVEL
To: SANDISK TECHNOLOGIES, INC.,
Reel/Frame 034193/0853 →
Continuity (1)
Related Publication 20160093635A1 · Mar 31, 2016