Structure and method to form a FinFET device
A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.
1. A method for fabricating a FinFET device, the method comprising:
forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer;
etching the semiconductor layer to form a plurality of fin structures and to form a semiconductor layer gap in between the fin structures and the BOX layer;
depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region;
disposing offset spacers on vertical sidewalls of the sacrificial gate;
removing the sacrificial gate;
removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate region; and
fabricating a high-k dielectric metal gate structure overlaying the plurality of fin structures in the gate region.
2. The method according to claim 1 , further comprising:
performing ion implantation in the source and the drain regions to form a n-type or a p-type FinFET device.
3. The method according to claim 1 , further comprising:
etching the fin structures so that a width of the plurality of fin structures in the gate region is less than a width of the plurality of fin structures in the source and the drain regions.
4. The method according to claim 1 , further comprising:
forming high-k dielectric spacers on vertical sidewalls of the high-k dielectric metal gate structure and the plurality of fin structures.
5. The method according to claim 1 , further comprising:
forming a hardmask layer overlaying the semiconductor layer.
6. The method according to claim 1 , further comprising:
forming a metal silicide layer in the source and the drain regions.
7. The method according to claim 6 , wherein the metal silicide layer includes tungsten.
8. The method according to claim 1 , further comprising:
planarizing the high-k dielectric metal gate structure using chemical mechanical polishing (CMP).
9. The method according to claim 1 , wherein the thickness of the semiconductor layer gap is 10 nanometers.
10. The method according to claim 1 , wherein the semiconductor layer material is silicon (Si).
11. The method according to claim 1 , further comprising:
etching the fin structures in the gate region so that a horizontal width of the plurality of fin structures ranges from about 1 nanometer to about 3 nanometers.