Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same

1. A method for manufacturing a semiconductor device, the method comprising:

forming an organic planarization layer on top and side surfaces of a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, and the organic planarization layer comprises top and side surfaces;

forming a contact area oxide layer on the top and side surfaces of the organic planarization layer, wherein the contact area oxide comprises top and side surfaces;

removing a portion of the contact area oxide layer to expose the top surface of the organic planarization layer, wherein the organic planarization layer covers the plurality of gates so that the plurality of gates remains unexposed during the removing of the portion of the contact area oxide layer;

stripping the entire organic planarization layer to form a cavity over the top and side surfaces of the plurality of gates and between the side surfaces of the contact oxide layer;

patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity after the removing and stripping steps; and

depositing a conductive contact in a remaining portion of the cavity, wherein the depositing of the conductive contact in the remaining portion of the cavity is performed without any prior removal of the patterned direct lithographically-patternable gap dielectric.

2. The method according to claim 1 , wherein the direct lithographically-patternable gap dielectric comprises hydrogen silsesquioxane (HSQ).

3. The method according to claim 1 , wherein stripping the organic planarization layer is performed with at least one of oxygen plasma, nitrogen plasma or hydrogen plasma.

4. The method according to claim 1 , wherein the organic planarization layer is formed to height of greater than about 5 nm above the gates.

5. The method according to claim 1 , wherein removing the portion of the contact area oxide layer comprises lithography and etching to leave portions of the oxide layer at varying heights.

6. The method according to claim 5 , wherein a first portion of the contact area oxide layer at a first height corresponds to a middle of the line contact areaand a second portion of the contact area oxide layer at a second height corresponds to a metallization level contact area.

7. The method according to claim 1 , wherein the direct lithographically-patternable gap dielectric is patterned on more than one gate and to different heights on at least two gates.

8. The method according to claim 7 , wherein the conductive contact fills in a space in the cavity between adjacent gates including the direct lithographically-patternable gap dielectric on each gate.

9. The method according to claim 1 , wherein a top surface of the contact area oxide layer is level with a top surface of the organic planarization layer after removal of the portion of the contact area oxide layer.

10. The method according to claim 9 , wherein the direct lithographically-patternable gap dielectric is patterned on more than one gate and to a same height as the contact area oxide layer.

11. The method according to claim 10 , wherein the conductive contact fills in a space in the cavity between adjacent gates including the direct lithographically-patternable gap dielectric on each gate.

12. The method according to claim 1 , wherein the organic planarization layer includes an organic polymer.

13. The method according to claim 1 , wherein the organic planarization layer is free of silicon.

14. The method according to claim 1 , wherein an entire top surface of the organic planarization layer is exposed to remove the entire organic planarization layer as a result of the stripping process.

15. The method according to claim 1 , wherein the direct lithographically-patternable gap dielectric is selectively deposited over the at least one of the gates leaving portions of the cavity formed by the stripping unfilled.

16. A method for manufacturing a semiconductor device, the method comprising:

forming an organic planarization layer on top and side surfaces of a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, and the organic planarization layer comprises top and side surfaces;

forming a contact area oxide layer on the top and side surfaces of the organic planarization layer, wherein the contact area oxide comprises top and side surfaces;

removing a portion of the contact area oxide layer to expose a top surface of the organic planarization layer;

stripping the entire organic planarization layer to form a cavity over the top and side surfaces of the plurality of gates and between the side surfaces of the contact oxide layer, exposing an entirety of the top and side surfaces of all of the plurality of gates including the spacer layers thereon, on which the organic planarization layer was formed;

patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity; and

depositing a conductive contact in a remaining portion of the cavity, wherein the depositing ofthe conductive contact in the remaining portion of the cavity is performed without any prior removal ofthe patterned direct lithographically-patternable gap dielectric.