Forming 3D memory cells after word line replacement
Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.
1. A method of fabricating non-volatile storage, the method comprising:
forming alternating layers of a first material and a second material above a substrate having a major surface;
etching holes in the alternating layers of the first material and the second material, wherein the holes have sidewalls that extend vertically with respect to the major surface;
forming a region of silicon at bottoms of the holes;
forming a protective layer of a material other than silicon on the region of silicon at the bottoms of the holes;
forming a sacrificial material in the holes after forming the protective layer;
removing the layers of the first material while leaving in place the layers of the second material and the sacrificial material in the holes, leaving recesses where the first material was removed;
forming a conductive material in the recesses;
removing the sacrificial material from the holes after forming the conductive material in the recesses;
removing the protective layer from the region of silicon after removing the sacrificial material from the holes; and
forming charge storage regions and channels of memory cells in the holes after removing the sacrificial material and the protective layer, wherein the conductive material forms control gates of the memory cells.
2. The method of claim 1 , further comprising:
etching openings in the alternating layers of the first material and the second material, wherein removing the layers of the first material comprises:
introducing an etchant into the openings.
3. The method of claim 1 , further comprising:
depositing an etch stop layer on the sidewalls of the holes prior to forming the sacrificial material in the holes, wherein the etch stop layer has etch selectivity with respect to the first material.
4. The method of claim 1 , further comprising:
forming a blocking layer of dielectric material in the recesses prior to forming the conductive material in the recesses.
5. The method of claim 1 , further comprising:
forming a blocking layer of dielectric material between the charge storage regions and the conductive material.
6. The method of claim 1 , wherein forming the charge storage regions comprises forming a charge storage layer that extends vertically in the holes, further comprising forming a tunnel dielectric layer on the charge storage layer, wherein forming the channels of memory cells comprises forming a semiconductor channel material on the tunnel dielectric layer.
7. The method of claim 1 , wherein forming the sacrificial material in the holes comprises:
forming an air gap within the sacrificial material.
8. The method of claim 1 , wherein the protective layer of the material other than silicon is a first protective material, and further comprising:
forming a second protective material other than the first protective material on sidewalls of the holes after removing the sacrificial material from the holes and prior to removing the first protective material from the region of silicon at the bottoms of the holes.
9. The method of claim 1 , wherein the first material has an etch selectivity with respect to the second material, wherein the second material is an insulator.
10. The method of claim 1 , wherein the first material is silicon oxide and the second material is silicon nitride.
11. The method of claim 1 , wherein the sacrificial material comprises either amorphous silicon or polysilicon.