IP Library Granted Patent US 9,907,129
Granted Patent B2
US 9,907,129 · App. 15/481,172 · Granted Feb 27, 2018

Multiple LED string dimming control

Inventors: Jeffrey Dann (Marathon, NY); Scott Dearborn (Brackney, PA)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H05B33/0815H05B33/083
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Quick Facts
Patent No.
US 9,907,129
App. No.
15/481,172
Granted
Feb 27, 2018
Kind
B2
Abstract

An integrated circuit device is configured to drive multiple LED strings. The device includes a switch mode power supply control circuit configured to generate primary and secondary power transistor control signals and receive at least one current sense signal and an output voltage sense signal. The device also includes an output compare circuit configured to generate a plurality of pulse width modulated signals and a logic circuit configured to generate signals for selecting a reference voltage and for activating an absorber mode. The signal for activating an absorber mode is to be shared with the secondary power transistor control signal. The logic circuit is to be synchronized with the output compare module.

Claims (34)

1. An integrated circuit device configured to drive multiple LED strings, the device comprising:

a switch mode power supply (SMPS) control circuit configured to generate primary and secondary power transistor control signals and receive at least one current sense signal and an output voltage sense signal;

an output compare circuit configured to generate a plurality of pulse width modulated signals; and

a logic circuit configured to generate signals for selecting a reference voltage and for activating an absorber mode;

wherein:

the signal for activating an absorber mode is configured to be shared with the secondary power transistor control signal; and

the logic circuit is configured to be synchronized with the output compare circuit.

2. The integrated circuit device of claim 1 , wherein the signal for activating an absorber mode overwrites the secondary power transistor control signal.

3. The integrated circuit device of claim 1 , further comprising a digital to analog converter configured to receive the signals for selecting the reference voltage.

4. The integrated circuit device of claim 1 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to reposition voltage during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

5. The integrated circuit device of claim 1 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to reposition voltage to a voltage level matching a voltage of a next LED string to be activated during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

6. The integrated circuit device of claim 1 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to absorb voltage to lower output voltage to a voltage level matching a voltage of a next LED string to be activated during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

7. The integrated circuit device of claim 1 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to absorb or reposition output voltage during a portion of a dimming cycle of the LED strings in which the LED strings are turned off based upon the logic circuit.

8. The integrated circuit device of claim 1 , wherein the logic circuit is further configured to alternately select the reference voltage from a overprotection voltage value and a candidate LED string voltage value, the candidate LED string voltage value corresponds to a next LED string voltage to be powered during a dimming cycle.

9. The integrated circuit device of claim 1 , wherein during a dimming cycle the logic circuit is further configured to alternately select the reference voltage from an overprotection voltage value and from a plurality of LED string voltages.

10. A system configured to drive multiple LED strings, the system comprising:

a SMPS control circuit configured to generate primary and secondary power transistor control signals and receive at least one current sense signal and an output voltage sense signal;

an output compare circuit configured to generate a plurality of pulse width modulated signals; and

a logic circuit configured to generate signals for selecting a reference voltage and for activating an absorber mode;

wherein:

the signal for activating an absorber mode is configured to be shared with the secondary power transistor control signal; and

the logic circuit is configured to be synchronized with the output compare circuit.

11. The system of claim 10 , wherein the signal for activating an absorber mode overwrites the secondary power transistor control signal.

12. The system of claim 10 , further comprising a digital to analog converter configured to receive the signals for selecting the reference voltage.

13. The system of claim 10 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to reposition voltage during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

14. The system of claim 10 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to reposition voltage to a voltage level matching a voltage of a next LED string to be activated during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

15. The system of claim 10 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to absorb voltage to lower output voltage to a voltage level matching a voltage of a next LED string to be activated during a portion of a dimming cycle of the LED strings in which the LED strings are turned off.

16. The system of claim 10 , wherein the SMPS control circuit is further configured to generate the primary and secondary power transistor control signals to absorb or reposition output voltage during a portion of a dimming cycle of the LED strings in which the LED strings are turned off based upon the logic circuit.

17. The system of claim 10 , wherein the logic circuit is further configured to alternately select the reference voltage from a overprotection voltage value and a candidate LED string voltage value, the candidate LED string voltage value corresponds to a next LED string voltage to be powered during a dimming cycle.

18. The system of claim 10 , wherein during a dimming cycle the logic circuit is further configured to alternately select the reference voltage from an overprotection voltage value and from a plurality of LED string voltages.

19. The system of claim 10 , further comprising:

a SMPS circuit coupled with the SMPS control circuit, the SMPS circuit comprising a primary filed effect transistor and a secondary field effect transistor that couples a shunt resistor connected with the output voltage of the SMPS circuit with ground; and

a plurality of LED strings coupled with an output of the SMPS circuit.

20. The system of claim 10 , further comprising a plurality of field effect transistors each associated with one of the LED strings and controlled by one of the plurality of pulse width modulated signals.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2017
From: DANN, JEFFREY; DEARBORN, SCOTT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 041889/0969 →
Continuity (2)
Provisional Application 62319494 · Apr 7, 2016
Related Publication 20170295618A1 · Oct 12, 2017