IP Library Granted Patent US 6,927,072
Granted Patent B2
US 6,927,072 · App. 10/093,909 · Granted Aug 9, 2005

Method of applying cladding material on conductive lines of MRAM devices

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Quick Facts
Patent No.
US 6,927,072
App. No.
10/093,909
Granted
Aug 9, 2005
Kind
B2
Abstract

A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Claims (24)

1. A method of fabricating a cladding region for use in a magnetoresistive memory device comprising the steps of:

providing a conductive line formed of conductive material and positioned proximate to a magnetoresistive memory device;

using a first electrochemical deposition bath to form a first barrier layer on the conductive line by one of immersion, electroless plating, and displacement plating; and

using a second electrochemical deposition bath to form a flux concentrating layer on the first barrier layer.

2. A method as claimed in claim 1 including in addition the step of using a third electrochemical deposition bath to form a second barrier layer on the flux concentrating layer.

3. A method as claimed in claim 2 wherein the step of using the third electrochemical deposition bath to form the second outside barrier layer includes using a second immersion bath wherein the second immersion bath includes one of platinum, palladium, ruthenium, rhodium, rhenium, iridium, and another suitable material more noble than the flux concentrating layer.

4. A method as claimed in claim 2 including in addition a step of controlling the second barrier layer thickness by controlling a time of immersion in the third electrochemical deposition bath.

5. A method as claimed in claim 1 wherein the step of using the second electrochemical deposition each include using one of immersion and electroless plating.

6. A method as claimed in claim 1 wherein the step of using the first electrochemical deposition bath to form the first barrier layer includes using a first immersion bath including one of platinum, palladium, ruthenium, rhodium, rhenium. iridium, and another suitable material more noble than the conductive material included in the conductive line.

7. A method as claimed in claim 1 wherein the step of using the second electrochemical deposition bath to form the flux concentrating layer includes using an electroless plating bath wherein the electroless plating bath includes one of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/Co/P, Ni/Fe/B/P.

8. A method as claimed in claim 1 including in addition a step of controlling the first barrier layer thickness by controlling a time of immersion in the first electrochemical deposition bath.

9. A method as claimed in claim 1 including in addition a step of controlling the flux concentrating layer thickness by controlling a time of immersion in the second electrochemical deposition bath.

10. A method as claimed in claim 1 wherein the conductive material forming the conductive line includes one of copper and aluminum.

11. A method of fabricating a cladding region for use in a magnetoresistive memory device comprising the steps of:

providing a conductive line formed of conductive material and positioned proximate to a magnetoresistive memory device;

displacement plating a first barrier layer on the conductive line;

using en electrochemical deposition bath, forming a flux concentrating layer on the first barrier layer; and

displacement plating a second barrier layer on the flux concentrating layer.

12. A method as claimed in claim 11 wherein the step of providing the conductive line includes providing a conductive line at least partially in a trench formed of dielectric material.

13. A method as claimed in claim 11 wherein the step of displacement plating the first barrier layer includes using a first bath including one of platinum, palladium, ruthenium, rhodium, rhenium,, iridium, and another suitable material more noble than the conductive material forming the conductive line.

14. A method as claimed in claim 11 wherein the step of displacement plating the second barrier layer includes using in the bath one of platinum, palladium, ruthenium, rhodium, rhenium, and iridium, and another suitable material more noble than material forming the flux concentrating layer.

15. A method as claimed in claim 11 including in addition the step of controlling the thicknesses of the first barrier layer, the flux concentrating layer, and the second barrier layer by controlling a time of immersion.

16. A method as claimed in claim 11 wherein the material forming the conductive line includes one of copper, titanium, and aluminum.

17. A method as claimed in claim 11 wherein the electrochemical deposition bath includes one of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/Co/P, and Ni/Fe/B/P.

Assignments (6)
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
RELEASE OF SECURITY INTEREST Recorded Jul 30, 2010
From: CITIBANK, N.A.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 024767/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 022597/0062 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2002
From: MOLLA, JAYNAL A.; D'URSO, JOHN; KYLER, KELLY; ENGEL, BRADLEY N.; GRYNKEWICK, GREGORY W.; RIZZO, NICHOLAS
To: MOTOROLA, INC.
Reel/Frame 012714/0126 →