Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
View Patent ↗A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.
1. A method for designing an integrated circuit, comprising the steps of:
(A) splitting a design layout of said integrated circuit into a plurality of tiles, wherein (i) said tiles each have a respective boundary, (ii) said design layout comprises a plurality of logic gates and (iii) said logic gates of a given set each have a respective logic input to be fixed at a first logical level;
(B) generating a list of said tiles;
(C) deleting from said list each of said tiles that does not contain at least one of said logical gates having at least one tied-to input;
(D) adding a plurality of tie-to cells to said design layout, wherein (i) said tie-to cells of a first set each generate a respective first tie-to signal at said first logical level, (ii) said first tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said logic inputs of said given set of said logic gates outnumber said tie-to cells of said first set; and
(E) routing said first tie-to signals from said tie-to cells of said first set to said logic inputs of said given set without crossing said boundaries.
2. The method according to claim 1 , wherein said tie-to cells of said first set each comprises a tie-high cell generating said first tie-to signal at a logical high level.
3. The method according to claim 1 , wherein said tie-to cells of said first set each comprises a tie-low cell generating said first tie-to signal at a logical low level.
4. The method according to claim 1 , wherein (i) said tie-to cells of a second set each generate a respective second tie-to signal at a second logical level, (ii) said second tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said first logical level is different than said second logical level.
5. The method according to claim 1 , further comprising the step of:
routing a second tie-to signal from a particular one of said tie-to cells of a second set to a particular one of said logic gates, wherein (i) said particular tie-to cell is in a first tile of said tiles, (ii) said particular logic gate is in a second tile of said tiles and (iii) said second tile is adjacent said first tile.
6. The method according to claim 1 , further comprising the step of:
routing a second tie-to signal from a particular one of said tie-to cells of said first set of said tie-to cells to a particular one of said logic inputs, wherein said second tie-to signal crosses one of said boundaries.
7. The method according to claim 1 , further comprising the step of:
generating at least one of said first tie-to signals using a resistive path to a power rail.
8. A method for designing an integrated circuit, comprising the steps of:
(A) splitting a design layout of said integrated circuit into a plurality of tiles, wherein (i) said tiles each have a respective boundary, (ii) said design layout comprises a plurality of logic gates and (iii) said logic gates of a given set each have a respective logic input to be fixed at a first logical level;
(B) adding a plurality of tie-to cells to said design layout, wherein (i) said tie-to cells of a first set each generate a respective first tie-to signal at said first logical level, (ii) said first tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said logic inputs of said given set of said logic gates outnumber said tie-to cells of said first set;
(C) routing said first tie-to signals from said tie-to cells of said first set to said logic inputs of said given set without crossing said boundaries; and
(D) marking each of said tiles that (i) contains at least one of said logical gates having at least one tied-to input and (ii) lacks available space to place corresponding cells of said tie-to cells to fix said tied-to input.
9. The method according to claim 8 , further comprising the step of:
checking available space in each of said tiles adjoining said tiles that have been marked to place said corresponding cells.
10. A storage medium for use in a computer to for design an integrated circuit, the storage medium recording a computer program that is readable and executable by the computer, when executed the computer program comprising the steps of:
(A) splitting a design layout of said integrated circuit into a plurality of tiles, wherein (i) said tiles each have a respective boundary, (ii) said design layout comprises a plurality of logic gates and (iii) said logic gates of a given set each have a respective logic input to be fixed at a first logical level;
(B) generating a list of said tiles;
(C) deleting from said list each of said tiles that does not contain at least one of said logical gates having at least one tied-to input;
(D) adding a plurality of tie-to cells to said design layout, wherein (i) said tie-to cells of a first set each generate a respective first tie-to signal at said first logical level, (ii) said first tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said logic inputs of said given set of said logic gates outnumber said tie-to cells of said first set; and
(E) routing said first tie-to signals from said tie-to cells of said first set to said logic inputs of said given set without crossing said boundaries.
11. The storage medium according to claim 10 , wherein said tie-to cells of said first set each comprises a tie-high cell generating said first tie-to signal at a logical high level.
12. The storage medium according to claim 10 , wherein said tie-to cells of said first set each comprises a tie-low cell generating said first tie-to signal at a logical low level.
13. The storage medium according to claim 10 , wherein (i) said tie-to cells of a second set each generate a respective second tie-to signal at a second logical level, (ii) said second tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said first logical level is different than said second logical level.
14. The storage medium according to claim 10 , further comprising the step of:
routing a second tie-to signal from a particular one of said tie-to cells of a second set to a particular one of said logic gates, wherein (i) said particular tie-to cell is in a first tile of said tiles, (ii) said particular logic gate is in a second tile of said tiles and (iii) said second tile is adjacent said first tile.
15. The storage medium according to claim 10 , further comprising the step of:
routing a second tie-to signal from a particular one of said tie-to cells of said first set of said tie-to to a particular one of said logic inputs, wherein said second tie-to signal crosses one of said boundaries.
16. The storage medium according to claim 10 , further comprising the step of:
generating at least one of said first tie-to signals using a resistive path to a power rail.
17. A storage medium for use in a computer to for design an integrated circuit, the storage medium recording a computer program that is readable and executable by the computer, when executed the computer program comprising the steps of:
(A) splitting a design layout of said integrated circuit into a plurality of tiles, wherein (i) said tiles each have a respective boundary, (ii) said design layout comprises a plurality of logic gates and (iii) said logic gates of a given set each have a respective logic input to be fixed at a first logical level;
(B) adding a plurality of tie-to cells to said design layout, wherein (i) said tie-to cells of a first set each generate a respective first tie-to signal at said first logical level, (ii) said first tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said logic inputs of said given set of said logic gates outnumber said tie-to cells of said first set;
(C) routing said first tie-to signals from said tie-to cells of said first set to said logic inputs of said given set without crossing said boundaries; and
(D) marking each of said tiles that (i) contains at least one of said logical gates having at least one tied-to input and (ii) lacks available space to place corresponding cells of said tie-to cells to fix said tied-to input.
18. The storage medium according to claim 17 , further comprising the step of:
checking available space in each of said tiles adjoining said tiles that have been marked to place said corresponding cells.