IP Library Granted Patent US 7,720,556
Granted Patent B2
US 7,720,556 · App. 11/315,959 · Granted May 18, 2010

Web-enabled solutions for memory compilation to support pre-sales estimation of memory size, performance and power data for memory components

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Quick Facts
Patent No.
US 7,720,556
App. No.
11/315,959
Granted
May 18, 2010
Kind
B2
Abstract

A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.

Claims (27)

1. A method, comprising:

providing an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component;

presenting a plurality of memory specification options to a user;

accepting at least one of the memory specification options from the user;

finding a plurality of selectable memories meeting the memory specification options accepted from the user;

presenting the selectable memories to the user;

accepting at least one memory selection from the user;

passing the at least one memory selection to a memory compiler and to an analyzer to produce memory configuration data; and

exporting the memory configuration data.

2. The method of claim 1 further comprising associating said network-based site with a script language that accepts single memory configuration data or multiple memory configuration data utilizing at least one URL parameter.

3. The method of claim 1 further comprising:

generating said memory configuration data in response to a particular user input, wherein said memory configuration data is generated using multiple input options to the memory compiler.

4. The method of claim 1 further comprising displaying the memory configuration data in a tabular form wherein the tabular form is sorted in conformance with a user preference.

5. The method of claim 1 further comprising tiling in order to meet large memory size requirements.

6. The method of claim 1 wherein said memory configuration data comprises data associated with said at least one memory component, wherein said at least one memory component comprises an LBRAM.

7. The method of claim 1 wherein said memory configuration data comprises data associated with said at least one memory component, wherein said at least one memory component comprises an SRAM.

8. A system, comprising a recordable medium embodying at least one control program that when executed by a data processing apparatus causes the system to instantiate and support a plurality of modules comprising:

an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data;

a memory selector that accepts a memory property specification from the user and presents zero or more selectable memories to the user wherein the user selects zero or more selected memories from the selectable memories;

a memory compiler that also accepts a memory property specification from the user, generates zero or more selectable compiled memories meeting the memory property specification and presents the selectable compiled memories to the user wherein the user selects zero or more selected memories from the selectable compiled memories;

a memory analyzer that supplies timing, size and power data for the selected memories wherein the selected memories comprise at least one selectable memory or at least one selectable compiled memory; and

a memory configuration exporting module that provides the user with at least one memory configuration describing at least one selected memory.

9. The system of claim 8 wherein the memory property specification is specified via a context sensitive menu or a batch file.

10. The system of claim 8 further comprising a script language that accepts single memory configuration data or multiple memory configuration data utilizing at least one URL parameter.

11. The system of claim 8 wherein said memory compiler accepts multiple compiler input options such that the memory configuration data is generated using multiple memory compiler input options.

12. The system of claim 8 further comprising a module for displaying said at least one memory selection into a table for display for said user via a graphical user interface and wherein the table is sorted in conformance with a user preference.

13. The system of claim 8 further comprising a memory tiler.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2006
From: CRISAN, CRISTIAN TEODOR; BALAJI, EKAMBARAM; VINKE, DAVID W.
To: LSI LOGIC CORPORTION
Reel/Frame 017802/0563 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2005
From: CRISAN, CRISTIAN TEODOR; BALAJI, EKAMABARAM
To: LSI LOGIC CORPORATION
Reel/Frame 017409/0148 →