Adaptive regulator for idle state in a charge pump circuit of a memory device
View Patent ↗An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
1. An apparatus comprising:
at least one memory element coupled to a modify node, a first node, and a read node, the read node to receive a voltage having a predetermined voltage level and to selectively provide information stored in the at least one memory element, the first node having a first capacitance and a first capacitance voltage level; and
an adaptive voltage generator coupled to the modify node to selectively modify information in the at least one memory element coupled to the modify node, wherein the adaptive voltage generator is configured to maintain the first node and the modify node at the predetermined voltage level when switching between a modify operation and a read operation in the at least one memory element.
2. The apparatus of claim 1 wherein the adaptive voltage generator is further configured to raise the first capacitance voltage level to a high voltage level greater than the predetermined voltage level after switching from the read operation to the modify operation in the at least one memory element.
3. The apparatus of claim 1 wherein the first capacitance is to coupled to a ground node to discharge the first capacitance voltage level when switching from the modify operation to the read operation in the at least one memory element.
4. The apparatus of claim 3 wherein the adaptive voltage generator is configured to maintain the first capacitance voltage level at the predetermined voltage level lower than a high voltage level after discharging of the first capacitance voltage level.
5. The apparatus of claim 1 wherein the predetermined voltage level is a read voltage level used during a read operation in the at least one memory element.
6. An apparatus comprising:
at least one memory element coupled to a modify node, a first node, and a read node, the read node to selectively provide information stored in the at least one memory element, the first node having a first capacitance and a first capacitance voltage level;
an adaptive voltage generator coupled to the modify node to selectively modify information in the at least one memory element coupled to the modify node, wherein the adaptive voltage generator is configured to maintain the first node at a predetermined voltage level when switching between a modify operation and a read operation in the at least one memory element;
a first switch coupled between the read node and the first node;
a second switch coupled between the first node and the modify node;
a third switch coupled between the first node and a second node;
a fourth switch coupled between the second node and a ground node; and
a second capacitance coupled between the second node and the ground node.
7. The apparatus of claim 6 wherein the adaptive voltage generator is configured to switch the first switch and the second switch to provide the predetermined voltage level to the second capacitance when switching from the read operation to the modify operation in the at least one memory element.
8. The apparatus of claim 7 wherein the adaptive voltage generator is configured to raise a second capacitance voltage level of the second capacitance to a high voltage level after switching from the read operation to the modify operation in the at least one memory element.
9. The apparatus of claim 6 wherein the fourth switch and the third switch are to couple the second capacitance to the ground node to discharge the second capacitance when switching from the modify operation to the read operation in the at least one memory element.
10. The apparatus of claim 9 wherein the adaptive voltage generator is configured to maintain the second capacitance voltage level at the predetermined voltage level lower than the high voltage level after discharging of the second capacitance.
11. The apparatus of claim 10 wherein the first node is coupled to the read node when the first switch switches.
12. An apparatus comprising:
a read node to receive a first voltage;
a modify node;
a switching stage coupled between the read node and the modify node, the switching stage including a first node; and
an adaptive voltage generator configured to apply a second voltage having a first value corresponding to a value of the first voltage to the modify node before the switching stage couples the first node to the modify node.
13. The apparatus of claim 12 wherein the adaptive voltage generator is further configured to raise second voltage to a second value higher than the first value after the switching stage couples the first node to the modify node.
14. The apparatus of claim 13 further comprising a switch configured to couple the first node to a second node when the first node is coupled to the modify node.
15. The apparatus of claim 14 wherein the adaptive voltage generator is further configured to reduce second voltage to a third value lower than the second value before the second node is discharged.
16. The apparatus of claim 12 further comprising at least one memory element coupled to at least one of the read node, the first node, and the modify node.
17. The apparatus of claim 12 wherein the switching stage includes a first switch coupled between the read node and the first node, and a second switch coupled between the first node and the modify node.
18. The apparatus of claim 17 wherein the switching stage is configured to close only one of the first and second switches at a time.
19. The apparatus of claim 17 further comprising a node to receive a control signal to control the first switch with the control signal and control the second switch with an inversion of the control signal.