One-time programmable non-volatile memory
View Patent ↗An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor.
1. An apparatus, comprising:
a semiconductor substrate of a first electrical conductivity type;
elongated diffused well regions in the semiconductor substrate, wherein the diffused well regions are of a second electrical conductivity type opposite the first electrical conductivity type; and
elongated electrical conductors each of which crosses the diffused well regions at respective locations of one-time programmable memory cells, wherein each of the memory cells comprises a respective antifuse structure between the respective diffused well region and the respective electrical conductor, each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance, and in the second state each of the memory cells comprises a respective rectifying junction between the respective diffused well region and the respective electrical conductor.
2. The apparatus of claim 1 , wherein the diffused well regions are arranged in parallel columns and the electrical conductors are arranged in parallel rows that are orthogonal to the diffused well regions.
3. The apparatus of claim 1 , wherein each of the memory cells comprises a respective first diffusion region of the first electrical conductivity type at a respective location in the respective elongated diffused well region that is self-aligned with respect to a first side of the respective electrical conductor.
4. The apparatus of claim 3 , wherein each of the memory cells comprises a respective second diffusion region of the first electrical conductivity type at a respective location in the respective diffused well region that is self-aligned with respect to a second side of the respective electrical conductor opposite the first side.
5. The apparatus of claim 4 , wherein in each of the memory cells the respective antifuse structure separates the respective electrical conductor from the respective first and second diffusion regions.
6. The apparatus of claim 4 , wherein in each of the memory cells the respective first and second diffusion regions are unconnected to any electrical biasing lines other than the respective diffused well region and the respective electrical conductor.
7. The apparatus of claim 1 , wherein each of the memory cells is free of any electrical biasing lines other than the respective diffused well region and the respective electrical conductor.
8. The apparatus of claim 1 , wherein each of the memory cells is free of any transistors.
9. The apparatus of claim 1 , wherein each of the electrical conductors comprises a respective metal layer.
10. The apparatus of claim 1 , wherein each of the electrical conductors comprises a respective polycrystalline silicon layer of the first electrical conductivity type.
11. The apparatus of claim 1 , wherein each of the antifuse structures comprises a dielectric layer.
12. The apparatus of claim 1 , further comprising a state sense circuit operable to sense the respective state of each of the memory cells based on current flow along an electrical path comprising the respective electrical conductor, the respective antifuse structure, and the respective diffused well region.
13. The apparatus of claim 1 , wherein each of the electrical conductors crosses each of the diffused well regions at respective locations of two or more of the memory cells.