Bottom-gate sonos-type cell having a silicide gate
View Patent ↗A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.
1. A field effect transistor comprising:
a first gate electrode of the transistor, wherein the first gate electrode comprises a first silicide layer;
a blocking dielectric layer comprising a first grown oxide layer above and in contact with the first silicide layer;
a dielectric charge storage layer above the blocking dielectric layer;
a tunneling dielectric layer above the dielectric charge storage layer; and
a first channel region of the transistor above the first grown oxide layer.
2. The field effect transistor of claim 1 wherein the first silicide layer comprises a silicide selected from a group consisting of cobalt silicide, chromium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
3. The field effect transistor of claim 1 wherein the first silicide layer is formed by reacting with amorphous or polycrystalline silicon.
4. The field effect transistor of claim 1 wherein a second gate electrode of a second transistor is disposed above the first channel region.
5. The field effect transistor of claim 4 wherein the second gate electrode comprises a second silicide layer.
6. The field effect transistor of claim 1 wherein the field effect transistor is a portion of a memory array.
7. The field effect transistor of claim 6 wherein the memory array is a monolithic three dimensional memory array.
8. A bottom-gate thin film transistor semiconductor device comprising:
a first amorphous or polycrystalline silicon layer;
a gate electrode of the thin film transistor, wherein the gate electrode comprises a silicide layer above and in contact with the first silicon layer;
a blocking dielectric layer above and in contact with the silicide layer;
a charge storage layer above the blocking dielectric layer;
a tunneling dielectric layer above the charge storage layer; and
a semiconductor channel of the transistor above the first dielectric layer.
9. The bottom-gate transistor of claim 8 wherein the silicide layer is selected from a group consisting of cobalt silicide, chromium silicide, titanium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
10. The bottom-gate transistor of claim 8 wherein the charge storage layer comprises a dielectric charge storage layer.
11. The bottom-gate transistor of claim 8 wherein a memory cell comprises the transistor.
12. The bottom-gate transistor of claim 11 wherein the memory cell is a portion of a memory array.
13. The bottom-gate transistor of claim 12 wherein the memory array is a monolithic three dimensional memory array.
14. The bottom-gate transistor of claim 8 wherein the blocking dielectric layer is a grown oxide.
15. A thin film transistor memory device comprising:
a first gate electrode of the thin film transistor formed above a substrate, wherein the gate electrode comprises a first silicide layer formed by consuming at least a portion of an amorphous or polycrystalline silicon layer;
a charge storage stack in contact with the first silicide layer; and
a semiconductor channel region in contact with the charge storage stack.
16. The thin film transistor of claim 15 wherein the charge storage stack is over the gate electrode and the semiconductor channel region is over the charge storage stack.
17. The thin film transistor of claim 16 wherein the charge storage stack comprises:
a blocking dielectric layer;
a dielectric charge storage layer; and
a tunneling dielectric layer.
18. The thin film transistor of claim 17 wherein the blocking dielectric layer is a grown oxide.
19. The thin film transistor of claim 15 wherein a memory cell comprises the transistor.
20. The thin film transistor of claim 19 wherein the memory cell is a portion of a first memory level of memory cells, the first memory level formed at a first height above the substrate.
21. The thin film transistor of claim 20 wherein the first memory level is a portion of a monolithic three dimensional memory array.
22. The thin film transistor of claim 20 wherein the substrate comprises monocrystalline silicon.
23. A monolithic three dimensional memory array comprising:
a first memory level comprising a first plurality of bottom-gate thin film transistors, wherein each transistor comprises a gate electrode comprising a silicide layer; and
a second memory level comprising a second plurality of bottom-gate transistors monolithically formed above the first memory level;
wherein each of the first plurality of bottom-gate thin film transistors further comprises:
a dielectric charge storage stack; and
a channel region;
wherein the silicide layer of each of the first plurality of bottom-gate thin film transistors is in contact with the dielectric charge storage stack.
24. The monolithic three dimensional memory array of claim 23 wherein each silicide layer is formed by consuming at least a portion of an amorphous or polycrystalline silicon layer.
25. The monolithic three dimensional memory array of claim 23 wherein each of the first bottom-gate thin film transistors comprises source and drain regions doped by ion implantation.
26. The monolithic three dimensional memory array of claim 25 wherein at least some of the first bottom-gate thin film transistors are NAND-connected in a series string.
27. The monolithic three dimensional memory array of claim 23 wherein the first memory level is formed above a substrate, the substrate comprising monocrystalline silicon.
28. A monolithic three dimensional array comprising:
a) a first memory level formed above a substrate, the first memory level comprising:
i) a first plurality of gate stripes, each gate stripe comprising a silicide layer and extending in a first direction;
ii) a first plurality of channel stripes extending in a second direction different from the first direction, the first channel stripes formed above the first gate stripes;
iii) a charge storage stack contacting the silicide layer and located between the first plurality of gate stripes and the first plurality of channel stripes; and
b) a second memory level monolithically formed above the first memory level.
29. The monolithic three dimensional array of claim 28 wherein the silicide comprises a silicide selected from the group consisting of cobalt silicide, chromium silicide, titanium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
30. The monolithic three dimensional array of claim 28 wherein each of the first channel stripes comprises a plurality of series connected channel regions and source/drain regions.
31. The monolithic three dimensional array of claim 30 wherein the source/drain regions are doped by ion implantation.