Amplifier circuit
View Patent ↗An amplifier circuit for amplifying a high-frequency input signal comprises an amplifier stage, which amplifies the high-frequency input signal as a function of an operating point of the amplifier stage and generates an operating point-dependent signal, an observer stage, which replicates the amplifier stage and generates an observation signal, a regulator, which is supplied with the operating point-dependent signal and the observation signal, and an control element, which influences the operating point of the amplifier stage and is driven by the regulator, whereby the regulator drives the control element in such a way that the operating point of the amplifier stage is substantially independent of a level of the high-frequency input signal.
1. Amplifier circuit for amplifying a high-frequency input signal, the amplifier circuit comprising:
an amplifier stage that amplifies the high-frequency input signal as a function of an operating point of the amplifier stage and generates an operating point-dependent signal;
an observer stage that replicates the amplifier stage and generates an observation signal;
a regulator that is supplied with the operating point-dependent signal and the observation signal; and
a control element that influences the operating point of the amplifier stage and is driven by the regulator,
wherein the regulator drives the control element in such a way that the operating point of the amplifier stage is substantially independent of a level of the high-frequency input signal.
2. The amplifier circuit according to claim 1 , wherein the amplifier stage comprises:
a transistor;
a capacitive coupling element that is looped between an input terminal of the input signal and a control terminal of the transistor;
a bias signal-generating circuit that generates a bias signal that is applied at the control terminal of the transistor; and
a load element having at least one terminal, which is looped in series with a collector-emitter path or a drain-source path of the transistor between a supply voltage and a reference potential,
wherein the amplified input signal is applied at the at least one terminal of the load element and the signal, based on an operating point of the amplifier stage, is generated from the amplified input signal.
3. The amplifier circuit according to claim 2 , wherein a resistor is looped between the at least one terminal of the load element at which the amplified input signal is applied and a terminal at which the signal dependent on the operating point of the amplifier stage is applied.
4. The amplifier circuit according to claim 2 , wherein the observer stage comprises:
a transistor at whose control terminal the bias signal is applied and which replicates the transistor of the amplifier stage; and
a load element having at least one terminal, which is looped in series with the collector-emitter path or the drain-source path of the transistor of the observer stage between the supply voltage and the reference potential and which replicates the load element of the amplifier stage,
wherein the observation signal applied at the at least one terminal of the load element.
5. The amplifier circuit according to claim 2 , wherein the control element comprises a controllable resistor, which is looped between the control terminal of the transistor of the amplifier stage and the reference potential.
6. The amplifier circuit according to claim 5 , wherein the controllable resistor is a field-effect transistor.
7. The amplifier circuit according to claim 6 , wherein the field-effect resistor is a MOS field-effect transistor.
8. The amplifier circuit according to claim 5 , wherein the controllable resistor is a bipolar transistor.
9. The amplifier circuit according to claim 2 , wherein the bias signal-generating circuit generates the bias signal in such a way that the amplification factor of the amplifier circuit is substantially independent of temperature.
10. The amplifier circuit according to claim 1 , further comprising:
a first mixer, wherein the load element of the amplifier stage and the first mixer are looped in series between the supply voltage and a terminal of the transistor of the amplifier stage; and
a second mixer, wherein the load element of the observer stage and the second mixer are looped in series between the supply voltage and a terminal of the transistor of the observer stage, and wherein the second mixer replicates the first mixer.
11. The amplifier circuit according to claim 1 , further comprising:
a first cascode circuit, wherein the load element of the amplifier stage and the first cascode circuit are looped in series between the supply voltage and a terminal of the transistor of the amplifier stage; and
a second cascode circuit, wherein the load element of the observer stage and the second cascode circuit are looped in series between the supply voltage and a terminal of the transistor of the observer stage, and the second cascode circuit replicates the first cascode circuit.
12. The amplifier circuit according to claim 2 , wherein the transistor of the amplifier stage and the transistor of the observer stage are bipolar transistors.
13. The amplifier circuit according to claim 2 , wherein the transistor of the amplifier stage and the transistor of the observer stage are MOS transistors.
14. The amplifier circuit according to claim 1 , wherein the regulator and/or the control element are digital.
15. The amplifier circuit according to claim 1 , wherein the observer stage replicates the amplifier stage in such a way that there is a predefined ratio between elements of the amplifier stage and the corresponding elements of the observer stage relative to element parameters.