Cooperative charge pump circuit and method
View Patent ↗A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.
1. A circuit comprising:
a first multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages, said first multi-stage charge pump circuit independently operable to generate a first output voltage;
a second multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages, said second multi-stage charge pump circuit independently operable to generate a second output voltage; and
means for coupling, at times, the first multi-stage charge pump circuit to the second multi-stage charge pump circuit, to cooperatively generate a cooperative output voltage having a greater voltage or current than either can generate operating independently;
wherein one of the first, second, and cooperative output voltages is of opposite polarity than another one of the first, second, and cooperative output voltages.
2. The circuit as recited in claim 1 wherein the first and second output voltages have the same polarity.
3. The circuit as recited in claim 1 wherein said means for coupling comprises switch means for coupling the respective ends of the first and second multi-stage charge pump circuits together, to thereby couple the first and second multi-stage charge pump circuits in parallel.
4. The circuit as recited in claim 1 wherein:
in a first mode of operation, the first and second multi-stage charge pump circuits cooperate to generate the cooperative output voltage; and
in a second mode of operation, the first and second multi-stage charge pump circuits operate independently, one of the first and second output voltages being a positive output voltage and the other of the first and second output voltages being a negative output voltage.
5. The circuit as recited in claim 4 further comprising:
a memory array having word lines and bit lines, and having support circuitry for said word lines and bit lines responsive to the charge pump circuit;
wherein, in the first mode of operation, the cooperative output voltage is coupled to certain ones of the word lines and bit lines; and
wherein, in the second mode of operation, one of the first and second output voltages is coupled to certain ones of the word lines, and the other of the first and second output voltages is coupled to certain ones of the bit lines.
6. The circuit as recited in claim 5 wherein said means for coupling comprises a switch circuit including at least one transistor.
7. The circuit as recited in claim wherein said memory array comprises passive element memory cells.
8. The circuit as recited in claim 1 wherein the first and second output voltages have different magnitudes.
9. The circuit as recited in claim 1 wherein the first, second, and cooperating output voltages each have different magnitudes.
10. A circuit comprising:
a first multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages, said first multi-stage charge pump circuit independently operable to generate a first output voltage;
a second multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages, said second multi-stage charge pump circuit independently operable to generate a second output voltage; and
means for coupling, at times, the first multi-stage charge pump circuit to the second multi-stage charge pump circuit, to cooperatively generate a cooperative output voltage having a greater voltage or current than either can generate operating independently;
wherein said means for coupling comprises switch means for coupling one end of the first multi-stage charge pump circuit to one end of the second multi-stage charge pump circuit, to thereby couple the first and second multi-stage charge pump circuits in series.
11. A method comprising:
at times, independently operating a first multi-stage charge pump circuit to generate a first output voltage, said first multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages;
at times, independently operating a second multi-stage charge pump circuit to generate a second output voltage, said second multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages;
at other times, coupling the first multi-stage charge pump circuit to the second multi-stage charge pump circuit to cooperatively generate a cooperative output voltage having a greater voltage or current than either can generate operating independently;
wherein one of the first, second, and cooperative output voltages is of opposite polarity than another one of the first, second, and cooperative output voltages.
12. The method as recited in claim 11 wherein the first and second output voltages have the same polarity.
13. The method as recited in claim 11 wherein said coupling step comprises coupling, at certain times, the respective ends of the first and second multi-stage charge pump circuits together, to thereby couple the first and second multi-stage charge pump circuits in parallel.
14. The method as recited in claim 11 wherein:
in a first mode of operation, the first and second multi-stage charge pump circuits cooperate to generate the cooperative output voltage; and
in a second mode of operation, the first and second multi-stage charge pump circuits operate independently, one of the first and second output voltages being a positive output voltage and the other of the first and second output voltages being a negative output voltage.
15. The method as recited in claim 14 further comprising:
in the first mode of operation, coupling the single output voltage to certain ones of word lines and bit lines of a memory array; and
in the second mode of operation, coupling one of the first and second output voltages to certain ones of the word lines, and coupling the other of the first and second output voltages to certain ones of the bit lines.
16. A method comprising:
at times, independently operating a first multi-stage charge pump circuit to generate a first output voltage, said first multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages;
at times, independently operating a second multi-stage charge pump circuit to generate a second output voltage, said second multi-stage charge pump circuit comprising a plurality of series-connected directional pump stages;
at other times, coupling the first multi-stage charge pump circuit to the second multi-stage charge pump circuit to cooperatively generate a cooperative output voltage having a greater voltage or current than either can generate operating independently;
wherein said coupling step comprises coupling, at certain times, one end of the first multi-stage charge pump circuit to one end of the second multi-stage charge pump circuit, to thereby couple the first and second multi-stage charge pump circuits in series.
17. The method as recited in claim 11 wherein the first and second output voltages have different magnitudes.
18. The method as recited in claim 11 wherein the first, second, and cooperating output voltages each have different magnitudes.
19. The method as recited in claim 15 wherein said memory array comprises passive element memory cells.