Stacked-die package including substrate-ground coupling
View Patent ↗Method and apparatus are provided for semiconductor device packages. In an example, an apparatus can include a first semiconductor device, a ground pad situated on an uppermost portion of the first semiconductor device and configured to electrically couple portions of the first semiconductor device to aground potential, and a second semiconductor device having at least a portion in electrical communication with an uppermost face of the first semiconductor device through a first electrically-conductive adhesive. In an example, the first electrically-conductive adhesive can be electrically coupled to the ground bond pad on the first semiconductor device.
1. An apparatus comprising:
a first semiconductor device;
a ground pad situated on an uppermost portion of the first semiconductor device and configured to electrically couple portions of the first semiconductor device to a ground potential; and
a second semiconductor device having at least a portion in electrical communication with an uppermost face of the first semiconductor device through a first electrically-conductive adhesive, wherein the first electrically-conductive adhesive is electrically coupled to the ground bond pad on the first semiconductor device, and wherein the first electrically-conductive adhesive physically contacts the ground bond pad on the first semiconductor device.
2. The apparatus of claim 1 including:
a die-attach paddle in electrical communication with the first semiconductor device; and
a plurality of package pads located on at least two sides of the die-attach paddle and electrically isolated therefrom.
3. The apparatus of claim 2 , including:
a bond wire electrically coupling the ground pad to one of the plurality of package pads, the one of the plurality of package pads configured to couple to a ground potential; and
an encapsulant configured to cover the first and second semiconductor devices and the bond wire.
4. The apparatus of claim 1 , wherein a face of the first semiconductor device and a face of the second semiconductor device have dissimilar geometrical areas.
5. The apparatus of claim 1 , wherein the second semiconductor device is fabricated from a silicon-on-insulator material having a base portion electrically insulated from a semiconducting portion, the base portion being in electrical communication with the uppermost face of the first semiconductor device through the first electrically-conductive adhesive.
6. The apparatus of claim 1 , including:
an inter-layer spacer disposed between the first and second semiconductor devices, the inter-layer spacer having a first face and a second face, the first face of the inter-layer spacer being electrically coupled to the uppermost portion of the first semiconductor device through the first electrically-conductive adhesive; and
wherein the second semiconductor device includes at least a portion in electrical communication with the second face of the inter-layer spacer through a second electrically-conductive adhesive.
7. The apparatus of claim 6 including:
a die-attach paddle in electrical communication with the first semiconductor device; and
a plurality of package pads located on at least two sides of the die-attach paddle.
8. The apparatus of claim 7 , further comprising:
a plurality of bond wires, at least one of the plurality of bond wires configured to electrically couple the ground pad to one of the plurality of package pads; and
an encapsulant configured to cover the first and second semiconductor devices, and the plurality of bond wires.
9. The apparatus of claim 6 wherein a face of the first semiconductor device and a face of the second semiconductor device include substantially equal geometrical areas.