Microprocessor for executing byte compiled JAVA code
View Patent ↗A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.
1. A microprocessor comprising:
a processor;
a first module to execute a set of instructions in bytecode in the processor;
a RISC module to execute a set of instructions as microcode in the processor; and
a datapath in the processor shared by both modules, the datapath including a register file shared by both modules, the first module seeing a first portion of the register file as a circular operand stack and a further portion as storage registers, and the RISC module seeing register file as a register file.
2. The microprocessor of claim 1 wherein the register file includes a control bit for tracking which module is in operation.
3. The microprocessor of claim 1 wherein the register file includes a program counter containing the address of an instruction to be executed.
4. The microprocessor of claim 1 wherein the register file includes a local variable base address to store base address information for local variables in a method.
5. The microprocessor of claim 1 wherein the register file includes a stack pointer to track a location of the top of the operand stack.
6. The microprocessor of claim 1 wherein the register file includes a RISC stack pointer to point to a location where the RISC can temporarily store variables if the register file is full.
7. The microprocessor of claim 1 wherein the register file includes a status register having a pair of status bits that inform the RISC module to use a value of the top of the operand stack as a register operand when executing an instruction, each of the pair of status bits controlling a source or a destination operand.
8. The microprocessor of claim 7 wherein when the status bits are set, the RISC module disregards the source or destination operand and uses the contents of a predefined register as the source or destination operand.
9. The microprocessor of claim 7 wherein the status bits are set and cleared by a RISC program that replaces the bytecode instruction.
10. A microprocessor comprising:
a processor;
a first module to execute a set of instructions in bytecode in the processor;
a RISC module to execute a set of instructions as microcode in the processor, the RISC module including an interrupt handler; and
a datapath in the processor shared by both modules, the datapath including a register file shared by both modules, the register file having a local variable base address to store base address information for local variables in a method, the first module seeing a first portion of the plurality of the register file as a circular operand stack and a remaining portion of the plurality of elements as storage registers, and the RISC module seeing the register file as a register file.
11. The microprocessor of claim 10 wherein the register file includes a control bit for tracking which module is in operation.
12. The microprocessor of claim 11 wherein the register file includes a program counter containing an address of an instruction to be executed.
13. The microprocessor of claim 12 wherein the register file includes a program counter base register for storing an address of a new method to be invoked.
14. The microprocessor of claim 13 wherein the register file includes a stack pointer to track a location of a top of the operand stack.
15. The microprocessor of claim 14 wherein the register file includes a RISC stack pointer to point to a location where the RISC module can temporarily store variables if the register file is full.
16. The microprocessor of claim 10 wherein the register file includes a status register having a pair of status bits that inform the RISC module to use a value from on top of the operand stack as a register operand when executing an instruction, each of the pair of status bits controlling a source or a destination operand.
17. The microprocessor of claim 16 wherein when the status bits are set, the RISC module disregards the source or destination operand and uses the contents of a predefined register as the source or destination operand.
18. The microprocessor of claim 17 wherein the status bits are set and cleared by a RISC program that replaces the bytecode instruction.
19. A processor implemented method comprising:
executing a set of instruction as bytecode in the processor with a first module;
executing a set of instructions as microcode in the processor with a RISC module;
interrupting the processor when an instruction too complex for execution by the first module appears;
executing the complex instruction separately from other instructions in the RISC module; and
returning to the first module when the RISC module has finished executing the complex instruction.
20. The method of claim 19 wherein the interrupting the processor includes:
jumping to a predefined address and reading a new branch address;
executing a branch instruction to the new branch address in the RISC module; and
executing a return instruction to return to program execution using the first module.