IP Library Granted Patent US 9,614,661
Granted Patent B2
US 9,614,661 · App. 13/442,502 · Granted Apr 4, 2017

Differential interface for inter-device communication in a battery management and protection system

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Quick Facts
Patent No.
US 9,614,661
App. No.
13/442,502
Granted
Apr 4, 2017
Kind
B2
Abstract

A multi-cell battery stack includes a microcontroller and a string of battery management and protection IC devices connected to one another in a daisy chain configuration. Each battery management and protection IC device can include a communication interface circuit includes pairs of differential input signal lines, receivers including respective current comparator circuits to receive differential signals on the differential input signal lines, and transmitters to provide outgoing differential signals on the differential input signal lines. A digital circuit block allows signals to pass between the receivers and transmitters.

Claims (29)

1. A battery management and protection integrated circuit comprising a communication interface circuit that comprises:

a first pair of differential input signal lines;

a first receiver comprising a first current comparator circuit to receive incoming differential signals on the first pair of differential input signal lines;

a first transmitter to provide outgoing differential signals on the first pair of differential input signal lines;

a second pair of differential input signal lines;

a second receiver comprising a second current comparator circuit to receive incoming differential signals on the second pair of differential input signal lines;

a second transmitter to provide outgoing differential signals on the second pair of differential input signal lines; and

a digital circuit block that allows signals to pass from the first receiver to the second transmitter and that allows signals to pass from the second receiver to the first transmitter,

wherein each of the first and second current comparator circuits includes:

class AB voltage output stages to generate current signals based on differential current input signals; and

current mirrors to transfer the current signals generated by the class AB voltage output stages to a summing node so as to provide a digital voltage output based on the differential input current.

2. The battery management and protection integrated circuit of claim 1 wherein current consumption by each of the first and second current comparator circuits is no greater than 5 μA.

3. A battery management and protection integrated circuit comprising a communication interface circuit that comprises:

a first pair of differential input signal lines;

a first receiver comprising a first current comparator circuit to receive incoming differential signals on the first pair of differential input signal lines;

a first transmitter to provide outgoing differential signals on the first pair of differential input signal lines;

a second pair of differential input signal lines;

a second receiver comprising a second current comparator circuit to receive incoming differential signals on the second pair of differential input signal lines;

a second transmitter to provide outgoing differential signals on the second pair of differential input signal lines; and

a digital circuit block that allows signals to pass from the first receiver to the second transmitter in a transparent manner and that allows signals to pass from the second receiver to the first transmitter in a transparent manner,

wherein each of the first and second transmitters includes a driver control portion and digital push/pull output drivers.

4. The battery management and protection integrated circuit of claim 3 wherein each of the first and second receivers is operable in an idle mode or in a transmission mode, and wherein a respective threshold of the respective first or second current comparator circuit is switchable depending on whether the respective first or second receiver is operating in the idle mode or transmission mode.

5. The battery management and protection integrated circuit of claim 4 wherein a first threshold value is used during the transmission mode and a second threshold value, having a magnitude at least five times as great as a magnitude of the first threshold value, is used during the idle mode.

6. The battery management and protection integrated circuit of claim 4 wherein a first threshold value is used during the transmission mode and a second threshold value having a greater magnitude is used during the idle mode.

7. The battery management and protection integrated circuit of claim 6 wherein the second threshold value is at least 750 mV.

8. The battery management and protection integrated circuit of claim 4 wherein the respective threshold of the respective first or second current comparator circuit is based on a signal from the digital circuit block.

9. The battery management and protection integrated circuit of claim 3 wherein the digital circuit block is operable to provide a first enable/disable signal to turn on/off the first receiver and the first transmitter and to provide as second enable/disable signal to turn on/off the second receiver and the second transmitter.

10. The battery management and protection integrated circuit of claim 3 wherein the push/pull output drivers in the second transmitter are activated when the first receiver detects beginning of a data transmission.

11. The apparatus of claim 10 wherein the push/pull output drivers in the first transmitter are activated when the second receiver detects beginning of a data transmission.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2012
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 028202/0428 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: ROEPER, WOLFGANG; AHLENDORF, HENDRIK; SCHMIDT, FRIEDEMANN
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 028152/0932 →