Compact electrostatic discharge (ESD) protection structure
A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
1. An electrostatic discharge (ESD) protection device, comprising:
a field effect transistor (FET) having a drain, at least two gates and a source, wherein the drain thereof is coupled to a node of a circuit to be protected from an ESD event;
at least one diode coupled between the source of the FET and a power supply common;
a first resistor coupled between the at least two gates of the FET; and
a second resistor coupled to a one of the at least two gates and the power supply common.
2. The ESD protection device according to claim 1 , wherein one of the at least two gates is a trigger gate and another one of the at least two gates is a discharge gate.
3. The ESD protection device according to claim 1 , wherein the at least one diode are two diodes connected in series between the source of the FET and power supply common.
4. The ESD protection device according to claim 1 , wherein the power supply common is coupled to an electrical ground.
5. The ESD protection device according to claim 1 , wherein the FET, the at least one diode and the first and second resistors are fabricated on an integrated circuit die and coupled to the circuit node that is coupled to an external connection of the integrated circuit die.
6. The ESD protection device according to claim 5 , wherein a function of the external connection of the integrated circuit die is selected from the group consisting of an analog input, a digital input, an analog output, a digital output, an analog input/output, a digital input/output, a power connection, a bias input, and an external compensation capacitor.
7. The ESD protection device according to claim 1 , wherein the FET is a depletion-mode FET.
8. The ESD protection device according to claim 7 , wherein the depletion-mode FET is a high-electron-mobility transistor (HEMT).
9. The ESD protection device according to claim 8 , wherein the HEMT is a pseudomorphic HEMT (pHEMT).
10. The ESD protection device according to claim 8 , wherein the HEMT is a metamorphic HEMT (mHEMT).
11. The ESD protection device according to claim 8 , wherein the HEMT is an induced HEMT.
12. An electrostatic discharge (ESD) protection device, comprising:
a field effect transistor (FET) having a drain, at least two gates and a source, wherein the drain thereof is coupled to a node of a circuit to be protected from an ESD event;
at least one diode having an anode coupled with the source of the FET;
a first resistor coupled between the at least two gates of the FET; and
a second resistor coupled to a one of the at least two gates and a cathode of the at least one diode.
13. The ESD protection device according to claim 12 , wherein one of the at least two gates is a trigger gate and another one of the at least two gates is a discharge gate.
14. The ESD protection device according to claim 12 , wherein the at least one diode are two diodes connected in series.
15. The ESD protection device according to claim 12 , wherein the cathode of the at least one diode is coupled with an electrical ground.
16. The ESD protection device according to claim 12 , wherein the FET is a depletion-mode FET.
17. The ESD protection device according to claim 16 , wherein the depletion-mode FET is a high-electron-mobility transistor (HEMT).
18. The ESD protection device according to claim 17 , wherein the HEMT is a pseudomorphic HEMT (pHEMT) or a metamorphic HEMT (mHEMT).
19. The ESD protection device according to claim 17 , wherein the HEMT is an induced HEMT.
20. The ESD protection device according to claim 17 , wherein the FET, the at least one diode and the first and second resistors are fabricated on an integrated circuit die and coupled to the circuit node that is coupled to an external connection of the integrated circuit die.
21. The ESD protection device according to claim 20 , wherein a function of the external connection of the integrated circuit die is selected from the group consisting of an analog input, a digital input, an analog output, a digital output, an analog input/output, a digital input/output, a power connection, a bias input, and an external compensation capacitor.