IP Library Granted Patent US 9,385,583
Granted Patent B2
US 9,385,583 · App. 14/319,022 · Granted Jul 5, 2016

Circuit and method for operating a circuit

Inventors: Sven Jochmann (Dresden, DE); Lutz Dathe (Dresden, DE)
Assignee: Atmel Corporation
H02M1/06G05F1/56G05F1/575G11C5/141H02J1/10H02M2001/0032Y10T307/549
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Quick Facts
Patent No.
US 9,385,583
App. No.
14/319,022
Granted
Jul 5, 2016
Kind
B2
Abstract

In certain embodiments, a circuit comprises a first voltage source configured to provide a supply voltage at an output of the first voltage source for a subcircuit. The circuit further comprises at least one second voltage source configured to provide output voltage to supply the subcircuit when the first voltage source is deactivated. The circuit further comprises an evaluation circuit connectable to an output of the at least one second voltage source, to a control input of the at least one second voltage source, and to the output of the first voltage source. The evaluation circuit is configured to adjust, based on the supply voltage at the output of the first voltage source, an output voltage of the at least one second voltage source.

Claims (44)

1. A circuit comprising:

a first voltage source configured to provide a supply voltage at an output of the first voltage source for a subcircuit, the subcircuit configured to have:

an operating mode with an operating current through the subcircuit; and

a sleep mode with a reduced current in comparison to the operating current through the subcircuit; and

an evaluation circuit connectable to an output of at least one second voltage source, to a control input of the at least one second voltage source, and to the output of the first voltage source, the at least one second voltage source configured to provide an output voltage to supply the subcircuit, the evaluation circuit configured to:

adjust the output voltage of the at least one second voltage source via a control signal at the control input of the at least one second voltage source, the at least one second voltage source being activated in the sleep mode; and

adjust the output voltage of the at least one second voltage source based on an evaluation of the supply voltage at the output of the first voltage source, the first voltage source being activated in the operating mode and deactivated in the sleep mode.

2. The circuit of claim 1 , wherein:

the evaluation circuit has a current source as a load for an output of the at least one second voltage source; and

a current of the current source is on the order of the reduced current through the subcircuit.

3. The circuit of claim 1 , wherein the evaluation circuit has a comparator configured to compare the output voltage of the at least one second voltage source and the supply voltage of the first voltage source.

4. The circuit of claim 3 , wherein:

the evaluation circuit has an arithmetic logic unit configured to evaluate the output voltage of the at least one second voltage source and the supply voltage of the first voltage source; and

the arithmetic logic unit is connectable to an output of the comparator.

5. The circuit of claim 1 , wherein the evaluation circuit is configured to adjust the output voltage of the at least one second voltage source via a successive approximation.

6. The circuit of claim 1 , wherein the at least one second voltage source has a current source and a resistance device for generating a reference voltage.

7. The circuit of claim 6 , wherein the evaluation circuit is configured to match a temperature response of the current source as a function of an adjustment result.

8. The circuit of claim 1 , wherein:

the second voltage source has a resistance device with a variable resistance value for setting the output voltage of the at least one second voltage source;

the second voltage source has a transistor configured as a source follower or an emitter follower;

a control input of the transistor is connectable to the resistance device; and

a source or an emitter of the transistor is connectable to an output of the second voltage source.

9. The circuit of claim 1 , further comprising a semiconductor switch configured to switch the output voltage of the second voltage source to the output of the second voltage source.

10. A circuit comprising:

a first voltage source configured to provide a supply voltage at an output of the first voltage source for a subcircuit;

at least one second voltage source configured to provide an output voltage to supply the subcircuit when the first voltage source is deactivated; and

an evaluation circuit connectable to an output of the at least one second voltage source, to a control input of the at least one second voltage source, and to the output of the first voltage source, the evaluation circuit configured to adjust, based on the supply voltage at the output of the first voltage source, an output voltage of the at least one second voltage source.

11. The circuit of claim 10 , wherein:

the evaluation circuit has a current source as a load for an output of the at least one second voltage source; and

a current of the current source 1s on the order of a quiescent current through the subcircuit.

12. The circuit of claim 10 , wherein the evaluation circuit has a comparator configured to compare the output voltage of the at least one second voltage source and the supply voltage of the first voltage source.

13. The circuit of claim 12 , wherein:

the evaluation circuit has an arithmetic logic unit configured to evaluate the output voltage of the at least one second voltage source and the supply voltage of the first voltage source; and

the arithmetic logic unit is connectable to an output of the comparator.

14. The circuit of claim 10 , wherein the evaluation circuit is configured to adjust the output voltage of the at least one second voltage source via a successive approximation.

15. The circuit of claim 10 , wherein the at least one second voltage source has a current source and a resistance device for generating a reference voltage.

16. The circuit of claim 10 , wherein the subcircuit is configured to have an operating mode and a sleep mode, the first voltage source being activated in the operating mode, and the first voltage source being deactivated and the at least one second voltage source being activated in the sleep mode.

17. A method comprising:

supplying, in an operating mode, a subcircuit having a first voltage source with a supply voltage;

deactivating, in a sleep mode, the first voltage source and supplying the subcircuit with a second voltage source,

wherein, in the operating mode, an output voltage of the second voltage source is adjusted as a function of the supply voltage of the first voltage source.

18. The method of claim 17 , further comprising comparing the output voltage of the second voltage source and the supply voltage of the first voltage source.

19. The method of claim 17 , further comprising switching the output voltage of the second voltage source to the output of the second voltage source.

20. The method of claim 17 , further comprising storing values of the adjustment of the output voltage of the second voltage source in memory.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038375/0724 →
PATENT SECURITY AGREEMENT Recorded Nov 4, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 034160/0563 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2014
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 033302/0592 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2014
From: JOCHMANN, SVEN; DATHE, LUTZ
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 033302/0486 →
Priority Claims (1)
DE 102008053536 · Oct 28, 2008 · national
Continuity (3)
Continuation 12580711 · Oct 16, 2009
Provisional Application 61117398 · Nov 24, 2008
Related Publication 20140375130A1 · Dec 25, 2014