Initiating multiple data transactions on a system bus
Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.
1. A method comprising:
receiving, by a controller, first information from a first peripheral requesting a first data transaction, the first information received over a first communication link between the controller and the first peripheral;
receiving, by the controller, second information from a second peripheral requesting a second data transaction, the second information received over a second communication link between the controller and the second peripheral;
determining, by the controller, quality of service (QoS) values for the first and second transactions based on the first and second information;
determining, by the controller, first and second ranks for the first and second data transactions based on the first and second information; and
initiating, based on the first and second ranks and the QoS values, the first or second data transaction on a system bus.
2. The method of claim 1 , wherein the controller is a direct memory access (DMA) controller and the first and second communication links provide direct communication paths from the first and second peripherals to the DMA controller.
3. The method of claim 1 , where determining, by the controller, first and second ranks for the first and second data transactions further comprises:
using the first information to determine a state of a first transaction queue of the first peripheral;
using the second information to determine a state of a second transaction queue of the second peripheral; and
determining the first and second ranks of the first and second data transactions based on the determined states of the first and second transaction queues.
4. The method of claim 3 , where the state of the first or second transaction queue is an almost full state or almost empty state.
5. The method of claim 1 , where the first or second communication link is a fixed-width bus and the first or second information is encoded with a protocol.
6. A system comprising:
a system bus;
a first peripheral coupled to the system bus;
a second peripheral coupled to the system bus;
a controller coupled to the system bus, the controller configured to receive over a first communication link first information from the first peripheral requesting a first data transaction, and to receive over a second communication link second information from the second peripheral requesting a second data transaction;
determining, by the controller, quality of service (QoS) values for the first and second transactions based on the first and second information;
determine first and second ranks for the first and second data transactions based on the first and second information; and
initiate, based on the first and second ranks and the QoS values, the first or second data transaction on the system bus.
7. The system of claim 6 , wherein the controller is a direct memory access (DMA) controller and the first and second communication links provide direct communication paths from the first and second peripherals to the DMA controller.
8. The system of claim 6 , where using, by the controller, the first and second information to determine first and second ranks for the first and second data transactions further comprises:
using the first information to determine a state of a first transaction queue of the first peripheral;
using the second information to determine a state of a second transaction queue of the second peripheral; and
determining the first and second ranks of the first and second data transactions based on the determined states of the first and second transaction queues.
9. The system of claim 8 , where the state of the first or second transaction queue is an almost full state or almost empty state.
10. The system of claim 6 , where the first or second communication link is a fixed-width bus and the first or second information is encoded with a protocol.
11. A non-transitory, computer-readable medium storing instructions, which, when executed by one or more processors, causes the one or more processors to perform operations comprising:
receiving first information from a first peripheral requesting a first data transaction, the first information received over a first communication link;
receiving second information from a second peripheral requesting a second data transaction, the second information received over a second communication link;
determining quality of service (QoS) values for the first and second transactions based on the first and second information;
determining first and second ranks for the first and second data transactions based on the first and second information; and
initiating, based on the first and second ranks and the QoS values, the first or second data transaction on a system bus.
12. The computer-readable medium of claim 11 , wherein the controller is a direct memory access (DMA) controller and the first and second communication links provide direct communication paths from the first and second peripherals to the DMA controller.
13. The computer-readable medium of claim 11 , where using the first and second information to determine ranks for the first and second data transactions further comprises:
using the first information to determine a state of a first transaction queue of the first peripheral;
using the second information to determine a state of a second transaction queue of the second peripheral; and
determining the first and second ranks of the first and second data transactions based on the determined states of the first and second transaction queues.
14. The computer-readable medium of claim 13 , where the state of the first or second transaction queue is an almost full state or almost empty state.
15. The computer-readable medium of claim 11 , where the first or second communication link is a fixed-width bus and the first or second information is encoded with a protocol.
16. A system comprising:
an interface configured to couple to a direct communication link with a direct memory access (DMA) controller;
memory;
a processor operable to:
implement a transaction queue in the memory;
determine a state of the transaction queue;
generate quality of service (QoS) information indicating the state of the transaction queue;
transmit the QoS information using the interface; and
receive, from the DMA controller using the interface, access to a system bus according to the state of the transaction queue.
17. The system of claim 16 , where the information indicates a number of slots available in the transaction queue.