IP Library Granted Patent US 9,727,119
Granted Patent B2
US 9,727,119 · App. 14/530,518 · Granted Aug 8, 2017

Controlling power states of a device

Inventors: Dirk Haentzschel (Porschendorf, DE); Falk Hofmann (Dresden, DE)
Assignee: Atmel Corporation
G06F1/3253G06F1/3287G06F13/4282G06F1/26G06F1/3203G06F1/3206G06F1/3275G06F1/3296G11C5/148G11C2216/30Y02B60/1228Y02B60/1235
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Quick Facts
Patent No.
US 9,727,119
App. No.
14/530,518
Granted
Aug 8, 2017
Kind
B2
Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling power states of a device. In one aspect, a circuit is configured to perform operations comprising: receiving, on a data pin of an SPI control interface, a command to enter a reduced power mode; determining that a select signal on a select pin of the SPI control interface has been released; in response to receiving the command to enter the reduced power mode and determining that the select signal has been released, causing the circuit to enter the reduced power mode; determining that the select signal on the select pin of the SPI control interface has been asserted; and in response to determining that the select signal on the select pin has been asserted, causing the circuit to exit the reduced power mode.

Claims (59)

1. An electronic device comprising:

a serial peripheral interface (SPI) control interface comprising at least:

a data pin for communicating data; and

a select pin for selecting the SPI control interface from a plurality of SPI interfaces;

a first circuit configured to perform operations comprising:

receiving, from the data pin of the SPI control interface, a command to enter a first power mode;

determining that a select signal on the select pin of the SPI control interface has been released;

in response to receiving the command to enter the first power mode and determining that the select signal has been released, entering the first power mode from a second power mode, the first circuit using less power in the first power mode than in the second power mode;

determining that the select signal on the select pin of the SPI control interface has been asserted; and

in response to determining that the select signal on the select pin has been asserted, exiting the first power mode; and

a second circuit coupled to the select pin and configured to:

after the select signal has been released, when the first circuit enters the first power mode, reset by a rise of a wakeup clear signal;

in response to the assertion of the select pin and the rise of the wakeup clear signal, cause a rise of an output wakeup signal to start a wakeup procedure to bring the first circuit out of the first power mode, and

cause a fall of the wakeup signal by a fall of the wakeup clear signal to bring the first circuit into the second power mode,

wherein, after the assertion of the select pin, the select signal is released after the rise of the wakeup signal and before the fall of the wakeup signal.

2. The electronic device of claim 1 , the operations comprising: before receiving the command to enter the first power mode, using the select signal to enable the control interface and to select the electronic device from a plurality of electronic devices.

3. The electronic device of claim 2 , the operations comprising: after exiting the first power mode, using the select signal to enable the control interface and to select the electronic device from the plurality of electronic devices.

4. The electronic device of claim 1 , wherein the SPI control interface includes a clock pin, a data input pin, a data output pin, and the select pin.

5. The electronic device of claim 1 , wherein receiving the command to enter a first power mode comprises receiving the command from a microcontroller, and wherein the microcontroller comprises a processor and a memory storing instructions that, when executed by the processor, cause the microcontroller to release and assert the select signal to control a power mode of the electronic device.

6. The electronic device of claim 1 , wherein the second circuit comprises a flip-flop configured to, in response to the assertion of the select signal, toggle to cause the wakeup signal to rise to cause the first circuit to exit the first power mode and start the wakeup procedure.

7. The electronic device of claim 1 , wherein the second circuit comprises a flip-flop including a clock input tied to an output of a logic gate that receives as inputs the select signal on the select pin and a reset signal, and

wherein the flip-flop is configured to:

in response to the assertion of the select signal, toggle to cause the wakeup signal to rise; and

in response to a trigger of the reset signal, toggle to cause the wakeup signal to rise.

8. A microcontroller comprising:

a processor; and

a memory storing instructions that, when executed by the processor, cause the processor to perform operations comprising:

sending, to a data pin of a serial peripheral interface (SPI) control interface of an electronic device, a command to enter a first power mode;

after sending the command to enter the first power mode, releasing a select signal on a select pin of the SPI control interface, causing a first circuit of the electronic device to enter the first power mode from a second power mode, the first circuit of the electronic device using less power in the first power mode than in the second power mode;

after releasing the select signal on the select pin, when the first circuit of the electronic device enters the first power mode, resetting a second circuit of the electronic device by causing a rise of a wakeup clear signal, the second circuit being coupled to the select pin and configured to receive the select signal on the select pin;

asserting the select signal on the select pin, causing a rise of a wakeup signal from the second circuit to start a wakeup procedure for the first circuit to exit the first power mode; and

causing a fall of the wakeup clear signal to cause a fall of the wakeup signal to bring the electronic device into the second power mode,

wherein after the assertion of the select signal, the select signal is released after the rise of the wakeup signal and before the fall of the wakeup signal.

9. The microcontroller of claim 8 , the operations comprising: before sending the command to enter the first power mode, using the select signal to enable the control interface and to select the electronic device from a plurality of electronic devices.

10. The microcontroller of claim 9 , the operations comprising: after asserting the select signal on the select pin, using the select signal to enable the control interface and to select the electronic device from the plurality of electronic devices.

11. The microcontroller of claim 8 , wherein the control interface is a serial peripheral interface (SPI) control interface that includes a clock pin, a data input pin, a data output pin, and the select pin.

12. The microcontroller of claim 8 , wherein the operations comprise acting as a master module on a bus coupled to the control interface and selecting the electronic device for communications on the bus using the select signal.

13. The microcontroller of claim 8 , wherein the circuit comprises a flip-flop including a clock input tied to an output of a logic gate that receives as inputs the select signal on the select pin and a reset signal from the processor, and

wherein the operations comprise:

asserting the select signal to toggle the flip-flop to cause the wakeup signal to rise; and

triggering the reset signal to toggle the flip-flop to cause the wakeup signal to rise, causing the electronic device to exit the first power mode.

14. A method performed by an electronic device, the method comprising:

receiving, on a data pin of a serial peripheral interface (SPI) control interface, a command to enter a first power mode;

determining that a select signal on the select pin of the SPI control interface has been released;

in response to receiving the command to enter the first power mode and determining that the select signal has been released, causing a first circuit of the electronic device to enter the first power mode from a second power mode, the first circuit using less power in the first power mode than in the second power mode;

after the select signal has been released, when the first circuit enters the first power mode, resetting a second circuit of the electronic device by a rise of a wakeup clear signal;

determining that the select signal on the select pin of the SPI control interface has been asserted, the second circuit being coupled to the select pin and configured to receive the select signal on the select pin;

in response to an assertion of the select signal and the rise of the wakeup clear signal, causing a wakeup signal output by the second circuit to rise to start a wakeup procedure for the first circuit to exit the first power mode; and

causing a fall of the wakeup signal by a fall of the wakeup clear signal to bring the first circuit into the second power mode,

wherein, after the assertion of the select signal, the select signal is released after the rise of the wakeup signal and before the fall of the wakeup signal.

15. The method of claim 14 , comprising: before receiving the command to enter the first power mode, using the select signal to enable the control interface and to select the electronic device from a plurality of electronic devices.

16. The method of claim 15 , comprising: after exiting the first power mode, using the select signal to enable the control interface and to select the electronic device from the plurality of electronic devices.

17. The method of claim 14 , wherein the control interface is a serial peripheral interface (SPI) control interface that includes a clock pin, a data input pin, a data output pin, and the select pin.

18. The method of claim 14 , wherein receiving the command to enter a first power mode comprises receiving the command from a microcontroller, and wherein the microcontroller comprises a processor and a memory storing instructions that, when executed by the processor, cause the microcontroller to release and assert the select signal to control a power mode of the electronic device.

19. The method of claim 14 , wherein the second circuit comprises a flip-flop, and wherein causing a rise of a wakeup signal comprises toggling the flip-flop to cause the wakeup signal to rise in response to the assertion of the select signal.

20. The method of claim 14 , wherein the second circuit comprises a flip-flop including a clock input tied to an output of a logic gate that receives as inputs the select signal on the select pin and a reset signal, and

wherein causing a rise of a wakeup signal comprises:

in response to the assertion of the select signal, toggling the flip-flop to cause the wakeup signal to rise; and

in response to a trigger of the reset signal, toggling the flip-flop to cause the wakeup signal to rise.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2015
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 035855/0317 →
PATENT SECURITY AGREEMENT Recorded Jun 16, 2015
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC., AS ADMINISTRATIVE AGENT, ISSUING BANK AND SWINGLINE LENDER
Reel/Frame 035918/0451 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2014
From: HAENTZSCHEL, DIRK; HOFMANN, FALK
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 034512/0375 →
Continuity (1)
Related Publication 20160124488A1 · May 5, 2016