Single wire communications using predictive host sampling window
Systems and techniques for single-wire communications are described. A described system includes a host device, and a slave device coupled with the host device via a single-wire bus. The host device can be configured to transmit synchronization information based on transitions over the single-wire bus. The slave device can be configured to detect the transitions on the single-wire bus, determine timing information of the host device based on a first transition of the transitions and a second transition of the transitions, determine a predicted start time of a host sampling window based on the timing information, and determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window. The charge operation can include drawing power from the single-wire bus to charge the device.
1. A device comprising:
a detector configured to detect transitions on a single-wire bus that are produced by a host, wherein the transitions provide synchronization information;
circuitry configured to (i) determine timing information of the host based on a first transition of the transitions and a second transition of the transitions, and (ii) determine a predicted start time of a host sampling window based on the timing information; and
a controller configured to determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window, wherein the charge operation comprises drawing power from the single-wire bus to charge the device.
2. The device of claim 1 , wherein the controller is configured to perform the charge operation before the predicted start time of the host sampling window based on the predicted charging duration reflecting that the charging operation is to complete before the predicted start time of the host sampling window.
3. The device of claim 1 , wherein the controller is configured to perform the charge operation after the predicted end time of the host sampling window based on the predicted charging duration reflecting that the charging operation is not to complete before the predicted start time of the host sampling window.
4. The device of claim 1 , wherein the charge operation comprises maintaining the single-wire bus at a high state.
5. The device of claim 1 , wherein the circuitry is configured to determine the timing information of the host based, at least in part, on a timing measurement from a first falling edge of the transitions to a second falling edge of the transitions.
6. The device of claim 1 , comprising:
a transmitter configured to transmit a bit of information requested by the host over the single-wire bus for at least a duration that spans the host sampling window,
wherein the transmitter is configured to pull the single-wire bus to a first voltage level if the bit of information represents a first bit state, and wherein the transmitter is configured to maintain the single-wire bus at a second voltage level if the bit of information represents a second bit state, wherein the second voltage level is higher than the first voltage level.
7. The device of claim 1 , comprising:
a non-volatile memory structure; and
a processor configured to perform an operation responsive to a command received over the single-wire bus, wherein the bit of information is retrieved from the non-volatile memory structure in response to the command.
8. A method comprising:
detecting, at a slave device, a first transition on a single-wire bus that is produced by a host device;
detecting a second transition on the single-wire bus that is produced by the host device, wherein the first transition and the second transition provide synchronization information;
determining timing information of the host device based on the first transition and the second transition;
determining, based on the timing information, a predicted start time of a host sampling window; and
determining, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window, wherein the charge operation comprises drawing power from the single-wire bus to charge the slave device.
9. The method of claim 8 , comprising:
performing the charge operation before the predicted start time of the host sampling window based on the predicted charging duration reflecting that the charging operation is to complete before the predicted start time of the host sampling window.
10. The method of claim 8 , comprising:
performing the charge operation after the predicted end time of the host sampling window based on the predicted charging duration reflecting that the charging operation is not to complete before the predicted start time of the host sampling window.
11. The method of claim 8 , transmitting a bit of information requested by the host device over the single-wire bus for at least a duration that spans the host sampling window, wherein transmitting the bit of information comprises:
pulling the single-wire bus to a first voltage level if the bit of information represents a first bit state; and
maintaining the single-wire bus at a second voltage level if the bit of information represents a second bit state, wherein the second voltage level is higher than the first voltage level.
12. A system comprising:
a host device; and
a slave device coupled with the host device via a single-wire bus,
wherein the host device is configured to transmit synchronization information based on transitions over the single-wire bus,
wherein the slave device is configured to (i) detect the transitions on the single-wire bus, (ii) determine timing information of the host device based on a first transition of the transitions and a second transition of the transitions, (iii) determine a predicted start time of a host sampling window based on the timing information, and (iv) determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window, wherein the charge operation comprises drawing power from the single-wire bus to charge the device.
13. The system of claim 12 , wherein the slave device is configured to perform the charge operation before the predicted start time of the host sampling window based on the predicted charging duration reflecting that the charging operation is to complete before the predicted start time of the host sampling window.
14. The system of claim 12 , wherein the slave device is configured to perform the charge operation after the predicted end time of the host sampling window based on the predicted charging duration reflecting that the charging operation is not to complete before the predicted start time of the host sampling window.
15. The system of claim 12 , wherein the charge operation comprises maintaining the single-wire bus at a high state.
16. The system of claim 12 , wherein the slave device is configured to determine the timing information of the host device based, at least in part, on a timing measurement from a first falling edge of the transitions to a second falling edge of the transitions.
17. The system of claim 12 , wherein the slave device is configured to transmit a bit of information requested by the host device over the single-wire bus for at least a duration that spans the host sampling window.
18. The system of claim 17 , wherein the slave device is configured to pull the single-wire bus to a first voltage level if the bit of information represents a first bit state, and wherein the slave device is configured to maintain the single-wire bus at a second voltage level if the bit of information represents a second bit state, wherein the second voltage level is higher than the first voltage level.
19. The system of claim 12 , wherein the slave device comprises:
a non-volatile memory structure; and
a processor configured to perform an operation responsive to a command received over the single-wire bus, wherein the bit of information is retrieved from the non-volatile memory structure in response to the command.
20. The system of claim 12 , wherein the host device comprises a dynamic clock generator, and a processor that is responsive to an output of the dynamic clock generator, wherein a timing of the transitions are responsive to the output of the dynamic clock generator.