Single-wire communications using iterative baud learning
Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate.
1. A method comprising: detecting transitions on a single-wire bus that are produced by a host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate, wherein determining the estimated baud rate comprises: resetting the capacitor in response to a detection of a first transition of the transitions; charging the capacitor based on the charging rate; determining, in response to a detection of a second transition of the transitions, a comparison result based on whether a capacitor voltage associated with the capacitor is less than a reference voltage; and adjusting the charging rate based on the comparison result.
2. The method of claim 1 , wherein adjusting the charging rate based on the comparison result comprises:
increasing the charging rate if the capacitor voltage is less than the reference voltage; and
decreasing the charging rate if the capacitor voltage is not less than the reference voltage.
3. The method of claim 1 , wherein resetting the capacitor comprises switching on a transistor to discharge the capacitor.
4. The method of claim 1 , wherein determining the estimated baud rate comprises:
controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit,
wherein iteratively adjusting the charging rate comprises determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit.
5. The method of claim 1 , comprising:
using digital logic circuitry to sample a comparator output that is responsive to a reference voltage and a capacitor voltage associated with the capacitor, wherein the digital logic circuitry is configured to sample the comparator output based on detection of one of the transitions.
6. The method of claim 1 , wherein the transitions comprise falling edge transitions.
7. A device comprising: a detector operable to detect transitions on a single-wire bus that are produced by a host; a timing estimator configured to determine an estimated baud rate of the host based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and circuitry operable to communicate with the host based on the estimated baud rate, wherein the timing estimator is configured to (i) reset the capacitor in response to a detection of a first transition of the transitions, (ii) charge the capacitor based on the charging rate, (iii) determine, in response to a detection of a second transition of the transitions, a comparison result based on whether a capacitor voltage associated with the capacitor is less than a reference voltage, and (iv) adjust the charging rate based on the comparison result.
8. The device of claim 7 , wherein the timing estimator is configured to adjust the charging rate by increasing the charging rate if the capacitor voltage is less than the reference voltage, and wherein the timing estimator is configured to adjust the charging rate by decreasing the charging rate if the capacitor voltage is not less than the reference voltage.
9. The device of claim 7 , comprising:
a transistor coupled with the capacitor,
wherein the timing estimator is configured to reset the capacitor by switching on the transistor to discharge the capacitor.
10. The device of claim 7 , wherein the timing estimator is configured to determine the estimated baud rate by controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit, and wherein iteratively adjusting the charging rate comprises determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit.
11. The device of claim 7 , comprising:
digital logic circuitry configured to sample a comparator output that is responsive to a reference voltage and a capacitor voltage associated with the capacitor, wherein the digital logic circuitry is configured to sample the comparator output based on detection of one of the transitions.
12. The device of claim 7 , wherein the transitions comprise falling edge transitions.
13. The device of claim 7 , comprising:
a non-volatile memory structure; and
a processor configured to perform an operation responsive to a command received over the single-wire bus, wherein the operation comprises retrieving data from the non-volatile memory structure in response to the command, and wherein the processor is configured to cause the data to be transmitted to the host based on the estimated baud rate.
14. A system comprising: a host device; and a slave device coupled with the host device via a single-wire bus, wherein the slave device is configured to perform operations comprising: detecting transitions on a single-wire bus that are produced by the host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate, wherein determining the estimated baud rate comprises: resetting the capacitor in response to a detection of a first transition of the transitions; charging the capacitor based on the charging rate; determining, in response to a detection of a second transition of the transitions, a comparison result based on whether a capacitor voltage associated with the capacitor is less than a reference voltage; and adjusting the charging rate based on the comparison result.
15. The system of claim 14 , wherein adjusting the charging rate based on the comparison result comprises:
increasing the charging rate if the capacitor voltage is less than the reference voltage; and
decreasing the charging rate if the capacitor voltage is not less than the reference voltage.
16. The system of claim 14 , wherein resetting the capacitor comprises switching on a transistor to discharge the capacitor.
17. The system of claim 14 , wherein determining the estimated baud rate comprises:
controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit,
wherein iteratively adjusting the charging rate comprises determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit.