Frequency control data synchronization
In an embodiment, a circuit includes a synchronizer configured to generate a trigger signal synchronized to a reference clock. A synthesizer is configured to synthesize a signal according to frequency control data in response to the trigger signal. A radio receiver is configured to process a carrier signal according to the synthesized signal. A phase measurement unit is configured to measure a first channel frequency response based on the processed carrier signal.
1. A circuit comprising:
a synchronizer configured to generate a trigger signal synchronized to a reference clock;
a synthesizer configured to synthesize a signal according to frequency control data in response to the trigger signal;
a radio receiver configured to process a carrier signal according to the synthesized signal and
to measure a first channel frequency response based on the processed carrier signal.
2. The circuit of claim 1 , further comprising:
a controller coupled to the synthesizer and configured to receive the frequency control data from a register and route a command to the synthesizer in response to the trigger signal.
3. The circuit of claim 2 , where the controller further comprises:
a multiplexer having a first input coupled to the register and a second input coupled to an output of the multiplexer, wherein in response to the trigger signal the frequency control data is routed to the controller.
4. The circuit of claim 3 , wherein the circuit further comprises:
a sigma/delta modulator coupled to the output of the multiplexer and configured to command the synthesizer based on the frequency control data.
5. The circuit of claim 2 , where the trigger signal is a periodic signal that has a constant period over channel center frequency changes.
6. The circuit of claim 5 , where the period is equal to a multiple of a phase measurement period used to measure the first channel frequency response.
7. The circuit of claim 1 , where the circuit is included in a first node of a radio network and further comprises:
a processor configured to:
estimate a phase offset and phase offset drift based on the first channel frequency response and a second channel frequency response measured by a second node of the radio network;
estimating a ranging channel frequency response based on the first channel frequency response;
estimating a distance offset based on the phase offset drift; and
estimating a distance between the first and second nodes based on the ranging channel frequency response and the distance offset.
8. The circuit of claim 7 , wherein estimating the distance between the first and second nodes based on the ranging channel frequency response and the distance offset, further comprises:
transforming the ranging channel frequency response into a ranging impulse response;
estimating the distance based on the ranging impulse response; and
correcting the distance based on the distance offset.
9. A method comprising:
generating, by a synchronizer, a trigger signal synchronized to a reference clock;
synthesizing, by a synthesizer, a signal according to frequency control data in response to the trigger signal;
processing, by a radio receiver, a carrier signal according to the synthesized signal; and
measuring, by the radio receiver, a first channel frequency response based on the processed carrier signal.
10. The method of claim 9 , further comprising:
receiving, by a controller, the frequency control data from a register; and
routing, by the controller, a command to the synthesizer in response to the trigger signal.
11. The method of claim 10 , where the trigger signal is generated in response to an overflow of a counter in the synchronizer, and where the counter is incremented based on the reference clock.
12. The method of claim 10 , wherein the trigger signal is a periodic signal that has a constant period.
13. The method of claim 12 , wherein the constant period is equal to a multiple of a phase measurement period used to measure the first channel frequency response.
14. The method of claim 9 , further comprising:
controlling, by a sigma/delta modulator, the synthesizer according to the frequency control data.
15. The method of claim 9 , where the method is performed by a first node of a radio network and further comprises:
estimating, by a processor, a phase offset and phase offset drift based on the first channel frequency response and a second channel frequency response measured by a second node of the radio network;
estimating, by the processor, a ranging channel frequency response based on the first channel frequency response;
estimating, by the processor, a distance offset based on the phase offset drift; and
estimating, by the processor, a distance between the first and second nodes using the ranging channel frequency response and the distance offset.
16. The method of claim 15 , wherein estimating the distance between the first and second nodes using the ranging channel frequency response and the distance offset, further comprises:
transforming, by the processor, the ranging channel frequency response into a ranging impulse response;
estimating, by the processor, the distance based on the ranging impulse response; and
correcting, by the processor, the distance based on the distance offset.
17. A system comprising:
a microcontroller;
an interface configured to receive a channel center frequency change command from the microcontroller;
a synchronizer coupled to a reference clock, the synchronizer configured to generate a trigger signal synchronized to the reference clock; and
a phase-locked loop (PLL) synthesizer coupled to the reference clock, the PLL synthesizer configured to synthesize a signal with a channel center frequency specified by the channel center frequency change command in response to the trigger signal;
a radio receiver coupled to the PLL synthesizer and configured to process a carrier signal according to the synthesized signal and
to measure a first channel frequency response based on the processed carrier signal.
18. The system of claim 17 , further comprising:
a controller coupled to the PLL synthesizer and configured to receive the channel center frequency change command from a register and route the command to the PLL synthesizer in response to the trigger signal generated by the synchronizer, where the trigger signal is a periodic signal having a constant period.
19. The system of claim 18 , where the channel center frequency change command includes frequency control data and the controller further comprises:
a multiplexer having a first input coupled to the register and a second input coupled to an output of the multiplexer, wherein in response to the trigger signal the frequency control data is routed to the controller.
20. The system of claim 19 , wherein the radio transceiver further comprises:
a sigma/delta modulator coupled to the output of the multiplexer and configured to command the PLL synthesizer based on the frequency control data.