IP Library Granted Patent US 9,978,691
Granted Patent B2
US 9,978,691 · App. 14/995,831 · Granted May 22, 2018

Semiconductor packages having wire bond wall to reduce coupling

Inventors: Shun Meen Kuo (Chandler, AZ); Paul R. Hart (Phoenix, AZ); Margaret A. Szymanowski (Chandler, AZ)
Assignee: NXP USA, INC.
H01L23/552H01L23/66H01L24/04H01L24/49H01L24/85H03F1/0288H03F3/195H03F3/211H01L24/45H01L24/48H01L2223/6611H01L2223/6644H01L2223/6655H01L2223/6661H01L2224/04042H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/48195H01L2224/48472H01L2224/49111H01L2224/49175H01L2224/85H01L2924/19107H01L2924/30111H03F2200/222H03F2200/387
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Quick Facts
Patent No.
US 9,978,691
App. No.
14/995,831
Granted
May 22, 2018
Kind
B2
Abstract

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

Claims (55)

1. A method of making a device housed within a package that includes a substrate, the method comprising the steps of:

defining an active circuit area over the top surface of the substrate;

positioning a first lead above the substrate and proximate to a first side of the package;

positioning a second lead above the substrate and proximate to a second side of the package;

positioning a third lead above the substrate and proximate to the first side of the package;

positioning a fourth lead above the substrate and proximate to the second side of the package;

attaching a first circuit over the top surface of the substrate within the active circuit area;

electrically coupling the first circuit between the first and second leads;

attaching a second circuit over the top surface of the substrate within the active circuit area and adjacent to the first circuit;

electrically coupling the second circuit between the third and fourth leads;

coupling a plurality of connection pads over the substrate in a row between the first circuit and the second circuit;

positioning a first terminal between the first lead and the third lead;

positioning a second terminal between the second lead and the fourth lead; and

electrically coupling a wire bond wall to the first terminal, the second terminal, or both the first and second terminals, wherein the wire bond wall includes a wire bond having a first end coupled to a first one of the connection pads and a second end coupled to a second one of the connection pads.

2. The method of claim 1 , wherein the wire bond wall is coupled between the first terminal and the second terminal, and the wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

3. The method of claim 1 , wherein the wire bond wall includes one or more additional wire bonds that electrically interconnect the connection pads.

4. The method of claim 1 , further comprising:

coupling one or more isolation structures to the top surface of the substrate, wherein an area over the top surface of the substrate within sidewalls of the one or more isolation structures defines the active circuit area; and

coupling a lid to the one or more isolation structures.

5. The method of claim 1 , wherein the substrate includes a conductive flange.

6. A method of making a device housed within a package that includes a substrate, the method comprising the steps of:

coupling a first circuit to a top surface of the substrate;

coupling a second circuit to the top surface of the substrate and adjacent to the first circuit;

arranging a plurality of connection pads over the substrate in a row between the first circuit and the second circuit; and

coupling a wire bond wall to the plurality of connection pads, wherein the wire bond wall includes a first wire bond having two ends coupled to a first set of two of the connection pads, and a second wire bond having two ends coupled to a second set of two of the connection pads.

7. The method of claim 6 , wherein at least one of the plurality of connection pads is electrically coupled to the substrate.

8. The method of claim 6 , further comprising:

positioning a first lead proximate to a first side of the package;

electrically coupling the first lead to the first circuit;

positioning a second lead proximate to a second side of the package;

electrically coupling the second lead to the first circuit;

positioning a third lead proximate to the first side of the package;

electrically coupling the third lead to the second circuit;

positioning a fourth lead proximate to the second side of the package;

electrically coupling the fourth lead to the second circuit;

positioning a first terminal over the first side of the package between the first lead and the third lead;

positioning a second terminal over the second side of the package between the second lead and the fourth lead; and

electrically coupling the wire bond wall to the first terminal, the second terminal, or both the first and second terminals.

9. The method of claim 8 wherein the first circuit includes a first power amplifier circuit, and the second circuit includes a second power amplifier circuit.

10. The method of claim 9 , wherein the first power amplifier circuit includes a first transistor, and the second power amplifier circuit includes a second transistor, and wherein at least some of the plurality of connection pads are positioned between the first transistor and the second transistor.

11. A method of making a portion of a Doherty amplifier housed within a package, the method comprising the steps of:

defining an active circuit area over the top surface of the substrate;

positioning a first lead above the substrate and proximate to a first side of the package;

positioning a second lead above the substrate and proximate to a second side of the package;

positioning a third lead above the substrate and proximate to the first side of the package;

positioning a fourth lead above the substrate and proximate to the second side of the package;

attaching a carrier amplifier over the top surface of the substrate within the active circuit area;

electrically coupling the carrier amplifier between the first and second leads;

attaching a peaking amplifier over the top surface of the substrate within the active circuit area and adjacent to the first circuit;

electrically coupling the peaking amplifier between the third and fourth leads;

coupling a plurality of connection pads over the substrate in a row between the carrier amplifier and the peaking amplifier; and

electrically coupling a wire bond wall to a first terminal positioned between the first and third leads, to a second terminal positioned between the second and fourth leads, or to both the first and second terminals, wherein the wire bond wall includes a wire bond having a first end coupled to a first one of the connection pads and a second end coupled to a second one of the connection pads.

12. The method of claim 11 , wherein the wire bond wall includes:

a first row of wire bonds that includes the first wire bond connected to the first set of two of the connection pads, and at least one additional first wire bond connected to a third set of the plurality of connection pads; and

a second row of wire bonds that includes the second wire bond connected to the second set of two of the connection pads, and at least one additional second wire bond connected to a fourth set of the plurality of connection pads, wherein the connection pads in the first and third sets of connection pads are positioned between the connection pads in the second and fourth sets of connection pads so that the wire bond wall forms a mesh.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2016
From: KUO, SHUN MEEN; HART, PAUL R.; SZYMANOWSKI, MARGARET A
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037493/0899 →
Continuity (3)
Division 14261387 · Apr 24, 2014
Continuation In Part 13929688 · Jun 27, 2013
Related Publication 20160211222A1 · Jul 21, 2016