Self-setting/resetting latch
A self-setting/resetting latch circuit is disclosed that includes resistive loads for inverters used for setting and clearing the latch. In a first embodiment, the resistive loads cause the latch circuit to automatically set in response to a power supply voltage going low. In an alternate embodiment, the latch circuit is configured to be self-resetting or self-clearing when the power supply voltage goes low by reversing the set and clear terminals of the latch circuit and selecting a different node to be the output terminal of the latch circuit. The disclosed latch circuit is small and robust and draws zero power in the set state.
1. A latch circuit comprising:
a first inverter coupled to a supply voltage and a clear terminal, the first inverter including a first resistive load; and
a second inverter cross-coupled to the first inverter and coupled to the supply voltage terminal and a set terminal, the second inverter including a second resistive load, wherein the first and second resistive loads cause the latch circuit to automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive loads is configured to adjust a threshold at which the latch circuit is automatically set or reset.
2. The latch circuit of claim 1 , wherein the latch circuit automatically sets or resets in response to the supply voltage falling below the threshold voltage.
3. The latch circuit of claim 1 , wherein the first inverter includes a first transistor and a first resistor, the first resistor coupled to a first drain terminal of the first transistor, and the second inverter includes a second transistor and a second resistor, the second resistor coupled to a second drain terminal of the second transistor.
4. The latch circuit of claim 3 , wherein the first transistor is an n-channel metal-oxide semiconductor (NMOS) transistor and the second transistor is a p-channel metal-oxide semiconductor (PMOS) transistor.
5. A memory cell comprising:
an interface;
a latch circuit coupled to the interface, the latch circuit comprising:
a first inverter coupled to a supply voltage and a clear terminal, the first inverter including a first resistive load; and
a second inverter cross-coupled to the first inverter and coupled to the supply voltage terminal and a set terminal, the second inverter including a second resistive load, wherein the first and second resistive loads cause the latch circuit to automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive loads is configured to adjust a threshold at which the latch circuit is automatically set or reset.
6. The memory cell of claim 5 , wherein the latch circuit automatically sets or resets in response to the supply voltage falling below the threshold voltage.
7. The memory cell of claim 5 , wherein the first inverter includes a first transistor and a first resistor, the first resistor coupled to a first drain terminal of the first transistor, and the second inverter includes a second transistor and a second resistor, the second resistor coupled to a second drain terminal of the second transistor.
8. The memory cell of claim 7 , wherein the first transistor is an n-channel metal-oxide semiconductor (NMOS) transistor and the second transistor is a p-channel metal-oxide semiconductor (PMOS) transistor.