Flash memory system using complementary voltage supplies
A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
1. A method of operating a flash memory device comprising a first set of memory cells and a second set of memory cells, the method comprising:
erasing the first set of memory cells, the erasing step comprising:
applying a first negative voltage to each coupling gate of the first set of memory cells;
applying a non-negative voltage to each word line and bit line of the first set of memory cells; and
applying a first positive voltage to each erase gate of the first set of memory cells; and
inhibiting the erasing of the second set of memory cells by applying a second positive voltage to each coupling gate of the second set of memory cells.
2. The method of claim 1 , wherein the step of applying a second positive voltage occurs concurrently or at approximately the same time as the step of applying a first negative voltage and before the step of applying a first positive voltage.
3. The method of claim 1 , wherein the first set of memory cells are split-gate flash memory cells and the second set of memory cells are split-gate flash memory cells.
4. The method of claim 2 , wherein the first set of memory cells are split-gate flash memory cells and the second set of memory cells are split-gate flash memory cells.