SPI interface with automatic slave select generation
A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.
1. A serial peripheral interface (SPI) module, comprising:
a transceiver comprising a clock line, a data line and at least one slave select line and being configurable to perform data transmission according to the SPI protocol; and
an interface circuit configured to operate in a first operating mode and in a second operating mode, wherein in the first operating mode, the slave select line must be controlled manually and in the second operating mode upon a request to transfer data to a slave device, the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated and maintained asserted for a plurality of clock cycles while data is transferred.
2. The module of claim 1 , wherein, in the second operating mode, the interface circuit is further configured to maintain the slave select line as asserted until a transfer count reaches zero.
3. The module of claim 1 , wherein, in the second operating mode, the interface circuit is further configured to de-assert the slave select line a predetermined time after a final clock edge.
4. The module of claim 1 , wherein, in the second operating mode, the interface circuit is further configured to de-assert the slave select line one-half baud clock after a final clock edge.
5. The module of claim 1 , wherein the interface circuit is further configured to operate in a programmable size byte transfer mode and in a programmable packet transfer mode.
6. The module of claim 1 , wherein the interface circuit is further configured to operate in a programmable size byte transfer mode, wherein each byte comprises a programmable number of bits.
7. The module of claim 1 , wherein the interface circuit is further configured to operate in a programmable packet transfer mode, wherein:
a total number of bits to be transferred is programmable;
a first parameter defines the number of 8-bit bytes to be transferred for a packet; and
a second parameter defines the number of bits of a last transfer for the packet.
8. The module of claim 1 , wherein, in the second operating mode, the interface circuit is further configured to assert the slave select line based upon a transfer count including a nonzero value.
9. The module of claim 1 , wherein the interface circuit is further configured to assert the slave select line upon determination of an override of the automatic slave select mode.
10. The module of claim 1 , wherein the interface circuit is further configured to:
assert the slave select line upon determination of an override of the automatic slave select mode; and
after removal of the override of the automatic slave select mode, evaluate a transfer count to determine whether to de-assert the slave select line.
11. A microcontroller comprising a module according to claim 1 .
12. A method of serial protocol interface data transfer according to the SPI protocol, comprising:
communicating from a master element to a slave element using a clock line, a data line and at least one slave select line; and
programming the master to operate in an automatic slave select mode;
when operating in the automatic slave select mode, upon a request to transfer data to a slave device including automatically asserting the slave select line at least one clock before a first clock edge is generated and maintained asserted for a plurality of clock cycles while data is transferred.
13. The method of claim 12 , further comprising maintaining the slave select line as asserted until a transfer count reaches zero.
14. The method of claim 12 , further comprising de-asserting the slave select line a predetermined time after a final clock edge.
15. The method of claim 12 , further comprising de-asserting the slave select line one-half baud clock after a final clock edge.
16. The method of claim 12 , further comprising operating in a programmable size byte transfer mode and in a programmable packet transfer mode.
17. The method of claim 12 further comprising operating in a programmable size byte transfer mode, wherein each byte comprises a programmable number of bits.
18. The method of claim 12 , further comprising operating in a programmable packet transfer mode, wherein:
a total number of bits to be transferred is programmable;
a first parameter defines the number of 8-bit bytes to be transferred for a packet; and
a second parameter defines the number of bits of a last transfer for the packet.
19. The method of claim 12 , further comprising asserting the slave select line based upon a transfer count including a nonzero value.
20. The method of claim 12 , further comprising asserting the slave select line upon determination of an override of the automatic slave select mode.
21. The method of claim 12 , further comprising:
asserting the slave select line upon determination of an override of the automatic slave select mode; and
after removal of the override of the automatic slave select mode, evaluating a transfer count to determine whether to de-assert the slave select line.
22. A microcontroller comprising a serial peripheral interface (SPI) module, wherein the SPI module comprises:
a transceiver comprising a clock line, a data line and at least one slave select line and being configurable to perform data transmission according to the SPI protocol; and
an interface circuit configured to operate in in an automatic slave select operating mode, in which upon a request to transfer data to a slave device issued by the microcontroller to the SPI module, the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge and associated data is generated without requiring additional software to assert the slave select line and maintained asserted for a plurality of clock cycles while data is transferred.