Security extensions for non-volatile memory
The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.
1. A memory system comprising:
memory;
a memory controller coupled to the memory and operable to:
receive a memory address and write data;
determine that the memory address accesses a secure data region in the non-volatile memory;
responsive to the determining, differentially expand the write data, wherein each bit of write data is converted to an m-bit counterpart and m is a positive integer greater than one; and
write the expanded write data to the secure data region at the memory address.
2. The memory system of claim 1 , further comprising:
responsive to the determining, differentially expanding and scrambling the write data.
3. The memory system of claim 1 , further comprising:
a register operable to store data indicating a size of the secure data region in the memory.
4. The memory system of claim 1 , wherein the memory controller is further operable to:
receive a memory address;
determine that the memory address accesses the secure data region in the memory;
responsive to the determining:
obtain differentially expanded read data from the memory at the memory address in the secure data region;
compress the differentially expanded read data to its pre-expanded form; and
provide access to the read data.
5. The memory system of claim 4 , further comprising:
checking the integrity of the read data.
6. The memory system of claim 4 , further comprising:
responsive to the determining, descrambling the read data.
7. The memory system of claim 1 , wherein the memory is non-volatile memory.
8. A memory controller comprising:
non-volatile memory;
a processor coupled to the non-volatile memory and operable to:
receive a memory address and write data;
determine that the memory address accesses a secure data region in the non-volatile memory;
responsive to the determining, differentially expand the write data, wherein each bit of write data is converted to an m-bit counterpart and m is a positive integer greater than one; and
write the expanded write data to the secure data region at the memory address.
9. The memory controller of claim 8 , further comprising:
responsive to the determining, differentially expanding and scrambling the write data.
10. The memory controller of claim 8 , further comprising:
a register operable to store data indicating a size of the secure data region in the non-volatile memory.
11. The memory controller of claim 8 , wherein the processor is further operable to:
receive the memory address;
determine that the memory address accesses the secure data region in the non-volatile memory;
responsive to the determining:
obtain differentially expanded read data from the non-volatile memory at the memory address in the secure data region;
compress the differentially expanded read data to its pre-expanded form; and
provide access to the read data.
12. The memory controller of claim 8 , further comprising:
checking the integrity of the read data.
13. The memory controller of claim 8 , further comprising:
responsive to the determining, descrambling the read data.
14. A method comprising:
receiving, by a memory controller, a memory address and write data;
determining, by the memory controller, that the memory address accesses a secure data region in memory;
responsive to the determining:
differentially expanding the write data, wherein each bit of write data is converted to an m-bit counterpart and m is a positive integer greater than one; and
writing the expanded write data to the secure data region at the memory address.
15. The method of claim 14 , further comprising:
responsive to the determining, differentially expanding and scrambling the write data.
16. The method of claim 14 , further comprising:
storing, by a register in the memory controller, data indicating a size of the secure data region in the memory.
17. The method of claim 14 , further comprising:
receiving the memory address;
determining that the memory address accesses the secure data region in the memory;
responsive to the determining:
obtaining differentially expanded read data from the memory at the memory address in the secure data region;
compressing the differentially expanded read data to its pre-expanded form; and
providing access to the read data.
18. The method of claim 14 , further comprising:
checking the integrity of the read data.
19. A non-transitory, computer-readable storage medium having instructions stored thereon, which, when executed one or more processors, causes the one or more processors to perform operations comprising:
receiving, by a memory controller, a memory address and write data;
determining, by the memory controller, that the memory address accesses a secure data region in memory embedded in or coupled to the memory controller;
responsive to the determining:
differentially expanding the write data, wherein each bit of write data is converted to an m-bit counterpart and m is a positive integer greater than one; and
writing the expanded write data to the secure data region at the memory address.
20. The non-transitory, computer-readable storage medium of claim 19 , further comprising:
determining that the memory address accesses the secure data region in the memory;
responsive to the determining:
obtaining differentially expanded read data from the memory at the memory address in the secure data region;
compressing the differentially expanded read data to its pre-expanded form; and
providing access to the read data.