Microcontroller with digital delay line analog-to-digital converters and digital comparators
Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.
1. A microcontroller comprising:
a processor core;
memory;
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines; and
a first circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input;
a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals; and
a second circuit, the second circuit comprising a set of delay elements included in the differential digital delay lines configured to produce data to indicate a degree to which an input to the ADC is out of an input range.
2. The microcontroller according to claim 1 , wherein the digital comparator has a plurality of outputs selected from the group consisting of greater, less, equal, greater or equal, less or equal.
3. The microcontroller according to claim 1 , comprising a plurality of digital comparators, each digital comparator coupled with an output of the ADC and with an associated register, wherein each digital comparator comprises a first output indicating that the output of the ADC is greater than a value of the associated register and a second output indicating that the output of the ADC is less or equal than the value of the associated register.
4. The microcontroller according to claim 1 , further comprising an internal bus coupled with the output of digital delay line analog-to-digital converter and a first input of the at least one digital comparator.
5. The microcontroller according to claim 1 , wherein the other peripheral is a pulse width modulation module.
6. The microcontroller according to claim 1 , wherein the other peripheral is a pulse width modulation module and the output of the digital comparator is configured to directly drive voltage adjustments of the pulse width modulation circuit, bypassing software control.
7. The microcontroller according to claim 1 , wherein the ADC further comprises a third circuit, the third circuit comprising a set of delay elements included in the differential digital delay lines configured to calibrate a source to the differential digital delay lines.
8. The microcontroller according to claim 1 , wherein the first circuit is configured to measure a difference between an input voltage and a reference voltage.
9. The microcontroller according to claim 1 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines.
10. The microcontroller according to claim 1 , wherein:
the ADC further comprises a third circuit, the third circuit comprising a set of delay elements included in the differential digital delay lines configured to calibrate a source to the differential digital delay lines; and
the microcontroller further comprises a current source circuit configured to mirror reference currents to each of the differential digital delay lines, wherein the third circuit is configured to adjust the reference currents to minimize error.
11. The microcontroller according to claim 1 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the first circuit is configured to measure the differential current and generate data representing the differential voltage.
12. The microcontroller according to claim 1 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.
13. The microcontroller according to claim 1 , wherein each differential digital delay line includes a chain of current limited buffers.
14. The microcontroller according to claim 1 , wherein:
a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;
the ADC further comprises a latch; and
the latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.
15. The microcontroller according to claim 1 , further comprising a third circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the third circuit is configured to calibrate a source to the differential digital delay lines.