Granted Patent B2

US 9,997,252 · App. 15/706,586 · Granted Jun 12, 2018

Inventors: Xiao Yan Pi (Shanghai, CN); Xiaozhou Qian (Shanghai, CN); Kai Man Yue (Shanghai, CN); Yao Zhou (Shanghai, CN); Yaohua Zhu (Shanghai, CN)

Assignee: Silicon Storage Technology, Inc.

G11C16/28G11C7/062G11C7/12G11C7/14G11C16/08G11C16/24G11C29/025G11C2029/1204G11C2029/5006

Abstract

Claims (8)

1. A system for detecting leakage current that exceeds a threshold reference current on a bit line in a memory system, comprising

a first PMOS transistor comprising a source coupled to a voltage source and a drain for generating a threshold reference current;

a memory cell coupled to the drain of the first PMOS transistor through a bit line at a first node, wherein the memory cell and the bit line draw a leakage current;

a second PMOS transistor comprising a source coupled to the voltage source and a drain for generating a constant voltage at a second node; and

a comparator that receives the first node as an input and the second node as an input and generates an output indicating if the leakage current exceeds the threshold reference current.

2. The system of claim 1 , wherein the threshold reference current is a level of acceptable leakage current for the bit line.

3. The system of claim 1 , further comprising a controller.

4. The system of claim 3 , wherein the controller is configured to store an identifier of the bit line if the leakage current exceeds the threshold reference current.

Assignments (12)

Continuity (2)