IP Library Granted Patent US 10,528,324
Granted Patent B2
US 10,528,324 · App. 15/784,981 · Granted Jan 7, 2020

Virtual hybrid for full duplex transmission

Inventor: Dan Stiurca (Austin, TX)
Assignee: Microsemi Storage Solutions, Inc.
G06F7/501G06F5/01H03K17/687H04L5/1461H04B1/16
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,528,324
App. No.
15/784,981
Granted
Jan 7, 2020
Kind
B2
Abstract

Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.

Claims (39)

1. A circuit, comprising:

a first feedback resistor;

a second feedback resistor coupled to the first feedback resistor;

a first set of M unit transistors connected in parallel and coupled to the first feedback resistor; and

a second set of N unit transistors connected in parallel coupled to the second feedback resistor and to the first set of M transistors;

wherein the circuit is configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.

2. The circuit of claim 1 , wherein the circuit is configured to prevent all internal nodes from swinging more than a predetermined maximum amplitude.

3. The circuit of claim 1 , further comprising:

a scaling circuit configured to scale an output of the second feedback resistor and the second set of N transistors.

4. The circuit of claim 3 , further comprising:

a summer configured to combine an output of the scaling circuit with an output of the first feedback resistor and the first set of M transistors.

5. The circuit of claim 1 , wherein gates of the first set of M transistors are directly coupled to gates of the second set of N transistors.

6. The circuit of claim 1 , wherein the first feedback resistor is directly coupled to the first set of M transistors.

7. The circuit of claim 1 , wherein the second feedback resistor is directly coupled to the second set of N transistors.

8. The circuit of claim 1 , wherein the first feedback resistor is directly coupled to the second feedback resistor.

9. The circuit of claim 1 , further comprising:

a driver configured to drive gates of the first set of M transistors and gates of the second set of N transistors, based on the transmitted signal.

10. The circuit of claim 9 , wherein the driver comprises at least one of an operational amplifier or an operational transconductance amplifier.

11. The circuit of claim 1 , wherein the first set of M transistors are connected to each other in parallel.

12. The circuit of claim 1 , wherein the second set of N transistors are connected to each other in parallel.

13. A method for canceling a transmitted signal received by a circuit on a full duplex line, the method comprising:

receiving the transmitted signal on the full duplex line;

presenting the received transmitted signal to a non-inverting input of an amplifier;

presenting an output of the amplifier to a first set of M transistors each having a gate coupled to the output of the amplifier, a drain coupled to the non-inverting input of the amplifier through a first feedback resistor, and a source coupled to ground; and

presenting the output of the amplifier to a second set of N transistors each having a gate coupled to the output of the amplifier, a drain coupled to the non-inverting input of the amplifier through a second feedback resistor, and a source coupled to ground;

wherein a ratio of the second feedback resistor to the first feedback resistor is selected to cancel the received transmitted signal.

14. The method of claim 13 , further comprising:

scaling an output of the second feedback resistor, wherein the scaling is performed as part of the canceling.

15. The method of claim 14 , further comprising:

summing the scaled output of the second feedback resistor with an output of the first feedback resistor, wherein the summing is performed as part of the canceling.

16. The method of claim 13 , further comprising:

switching gates of the transistor sets based on the transmission signal.

17. The method of claim 12 wherein the first feedback resistor and a ratio of M to N are both selected to match an output resistance of the circuit to a resistance of the full duplex line.

18. The method of claim 12 wherein presenting the received transmitted signal to a non-inverting input of an amplifier comprises presenting the received transmitted signal to one of an operational amplifier and an operational transconductance amplifier.

19. The circuit of claim 1 further comprising:

an amplifier having a non-inverting input, an inverting input, and an output;

and wherein

the first set of M transistors each has a gate coupled to the output of the amplifier, a drain coupled to the non-inverting input of the amplifier through the first feedback resistor, and a source coupled to ground; and

the second set of N transistors each has a gate coupled to the output of the amplifier, a drain coupled to the non-inverting input of the amplifier through the second feedback resistor, and a source coupled to ground.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2017
From: STIURCA, DAN
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 044084/0528 →
Continuity (2)
Provisional Application 62410254 · Oct 19, 2016
Related Publication 20180107452A1 · Apr 19, 2018