Power module package and method of manufacturing the same
A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.
1. A method comprising:
coupling a semiconductor chip with a substrate;
coupling an electrode with the substrate;
mounting the substrate on a bottom mold die and connecting the bottom mold die to a top mold die, the top mold die:
defining a first space and a second space, the second space being separated from the first space,
the first space housing the semiconductor chip and, at least partially, surrounding a perimeter the second space, and
the second space housing the electrode; and
injecting an encapsulation material, such that the encapsulation material is injected into the first space and excluded from the second space,
the injected encapsulation material forming an encapsulation member coupled to and covering at least a portion of the substrate, the encapsulation member including a housing unit housing the electrode,
the electrode having a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate having a portion exposed within the open space, the encapsulation member having an open cross-section perpendicular to an upper surface of the substrate and aligned along an extension line intersecting the electrode.
2. The method of claim 1 , further comprising, prior to connecting the bottom mold die to the top mold die, forming a wiring member electrically connecting the semiconductor chip with the electrode.
3. The method of claim 2 , wherein the wiring member is housed within the first space and encapsulated within the encapsulation material.
4. The method of claim 2 , wherein forming the wiring member includes:
coupling the wiring member with the semiconductor chip via a first bonding member; and
coupling the wiring member with the substrate via a second bonding member.
5. The method of claim 1 , further comprising, prior to coupling the semiconductor chip with the substrate, disposing a bonding member on the substrate, the semiconductor chip being coupled to the substrate via the bonding member.
6. The method of claim 1 , further comprising, prior to coupling the electrode with the substrate, disposing a bonding member on the substrate, the electrode being coupled to the substrate via the bonding member.
7. The method of claim 1 , wherein the second space has a depth in the top mold die that is, relative to an upper surface of the substrate, greater than a depth of the first space in the top mold die.
8. The method of claim 1 , wherein the encapsulation member is formed such that the electrode has an exposed upper surface and an exposed portion of the conductive sidewall extending above the uppermost surface of the encapsulation member.
9. A method comprising:
coupling a semiconductor chip with a substrate;
coupling an electrode with the substrate;
forming a wiring member electrically coupling the semiconductor chip with the electrode;
mounting the substrate on a bottom mold die and connecting the bottom mold die to a top mold die, the top mold die:
defining a first space and a second space, the second space being separated from the first space,
the first space housing the semiconductor chip and completely surrounding a perimeter of the second space, and
the second space housing the electrode; and
injecting an encapsulation material, such that the encapsulation material is injected into the first space and excluded from the second space,
the injected encapsulation material forming an encapsulation member coupled to and covering at least a portion of the substrate, the encapsulation member including a housing unit housing the electrode,
the electrode having a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate having a portion exposed within the open space, the encapsulation member having an open cross-section perpendicular to an upper surface of the substrate and aligned along an extension line intersecting the electrode.
10. The method of claim 9 , wherein the wiring member includes one of:
a bonding clip;
a bonding ribbon; or
a bonding wire.
11. The method of claim 9 , further comprising, prior to coupling the electrode with the substrate, disposing a bonding member on the substrate, the electrode being coupled to the substrate via the bonding member.
12. The method of claim 9 , wherein the second space has a depth in the top mold die that is, relative to an upper surface of the substrate, greater than a depth of the first space in the top mold die.
13. A method comprising:
coupling a first semiconductor chip and a second semiconductor chip with a substrate;
coupling a first electrode and a second electrode arranged with the substrate;
mounting the substrate on a bottom mold die and connecting the bottom mold die to a top mold die, the top mold die:
defining a first space, a second space and a third space, the second space and the third space being separated from the first space,
the first space housing the first semiconductor chip and the second semiconductor chip and, at least partially, surrounding respective perimeters of the second space and third space, and
the second space housing the first electrode;
the third space housing the second electrode; and
injecting an encapsulation material, such that the encapsulation material is injected into the first space, excluded from the second space, an excluded from the third space,
the injected encapsulation material forming an encapsulation member coupled to and covering at least a portion of the substrate, the encapsulation member including a first housing unit housing the first electrode and a second housing unit housing the second electrode,
the first electrode and the second electrode each having a conductive sidewall exposed to the encapsulation member,
the first electrode having an upper surface and a portion of the conductive sidewall extending above the encapsulation member,
the conductive sidewall of the first electrode not being in contact with the first housing unit of the encapsulation member, such that there is open space of a first distance between the conductive sidewall of the first electrode and the first housing unit of the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member,
the conductive sidewall of the second electrode not being in contact with the second housing unit of the encapsulation member, such that there is open space of a second distance between the conductive sidewall of the second electrode and the second housing unit of the encapsulation member from the uppermost surface to the bottommost surface of the encapsulation member, the second distance being different from the first distance.
14. The method of claim 13 , wherein the upper surface of the second electrode is disposed higher than the uppermost surface of the encapsulation member relative to an upper surface of the substrate.
15. The method of claim 13 , further comprising, prior to connecting the bottom mold die to the top mold die:
forming a first wiring member electrically connecting the first semiconductor chip with the first electrode; and
forming a second wiring member electrically connecting the second semiconductor chip with the second electrode.
16. The method of claim 15 , wherein the first wiring member and the second wiring member are housed within the first space and encapsulated within the encapsulation material.
17. The method of claim 15 , wherein forming the first wiring member includes:
coupling the first wiring member with the first semiconductor chip via a first bonding member; and
coupling the first wiring member with the substrate via a second bonding member.
18. The method of claim 15 , wherein the first wiring member and the second wiring member respectively include one of:
a bonding clip;
a bonding ribbon; or
a bonding wire.
19. The method of claim 15 , further comprising, prior to coupling the first electrode and the second electrode with the substrate, disposing a first bonding member and a second bonding member on the substrate, the first electrode and the second electrode being respectively coupled to the substrate via the first bonding member and the second bonding member.
20. The method of claim 13 , wherein the second space and the third space have respective depths in the top mold die that are, relative to an upper surface of the substrate, greater than a depth of the first space in the top mold die.