High density three-dimensional integrated capacitors
A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
1 . A microelectronic element, comprising:
a substrate having an upper planar surface, an opposite lower planar surface, and a side surface, wherein the upper planar surface comprises a circuit element and wherein the upper planar surface and the lower planar surface are perpendicular to the side surface;
a first dielectric layer at least partially disposed in the substrate between the upper planar surface and the lower planar surface, the first dielectric layer comprising an undulating shape that has a first side and an opposite second side, wherein the undulating shape extends downwardly with respect to the upper planar surface and extends upwardly with respect to the lower planar surface when viewed from a perspective of the side surface;
a first electrically conductive layer disposed on the first side of the first dielectric layer, wherein the first electrically conductive layer conforms to the undulating shape of the first dielectric layer;
a second electrically conductive layer and a third electrically conductive layer disposed on the second side of the first dielectric layer, wherein the second and third electrically conductive layers conform to the undulating shape of the first dielectric layer;
a second dielectric layer disposed between the second electrically conductive layer and the third electrically conductive layer; and
a plurality of first electrodes electrically connected to the first electrically conductive layer, a second electrode electrically connected to the second electrically conductive layer, and a third electrode electrically connected to the third electrically conductive layer.
2 . The microelectronic element as claimed in claim 1 , wherein undulating portions of the first dielectric layer extend downwardly from the upper planar surface of the substrate to locations proximate to the lower planar surface.
3 . The microelectronic element as claimed in claim 1 , wherein the substrate is at a ground potential.
4 . The microelectronic element as claimed in claim 1 , wherein the substrate comprises silicon.
5 . The microelectronic element as claimed in claim 1 , wherein the second electrode is connected to an outer portion of the second electrically conductive layer; and
the third electrode is connected to an outer portion of the third electrically conductive layer.
6 . The microelectronic element as claimed in claim 5 , wherein:
the first electrically conductive layer, the second electrically conductive layer, the third electrically conductive layer, the first dielectric layer, and the second dielectric layer are disposed in one or more openings formed in the substrate; and
the plurality of first electrodes are connected to corresponding locations on the first electrically conductive layer that are radially inward from connection locations of the second and third electrodes to the second and third electrically conductive layers.
7 . The microelectronic element as claimed in claim 1 , wherein when the microelectronic element is in use, the plurality of first electrodes and the third electrode are connected with a first electric potential and the second electrode is connected with a second electric potential.
8 . The microelectronic element as claimed in claim 1 , wherein the undulating shape comprises a peak and a trough, and wherein the peak is closer to the upper planar surface than the trough.
9 . The microelectronic element as claimed in claim 1 , wherein the circuit element is disposed at and below the upper planar surface.